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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SIS | 2023-12-07 11:00 |
Aichi | Sakurayama Campus, Nagoya City University (Primary: On-site, Secondary: Online) |
Data Path Parallelization to Improve Performance of High-level Synthesized Sprite Drawing Hardware Yuka Otani, Akira Yamawaki (Kyutech)  SIS2023-24 |
A mobile terminal architecture which can dynamically reconfigure the optimal hardware for each application can achieve h... [more] | SIS2023-24 pp.1-6 |
| ICD, CPSY | 2015-12-18 14:30 |
Kyoto | Kyoto Institute of Technology | A Low Latency Distributed Routing Method for Random Topologies in HPC Networks Ryuta Kawano, Hiroshi Nakahara (Keio Univ.), Ikki Fujiwara (NII), Hiroki Matsutani, Hideharu Amano (Keio Univ.), Michihiro Koibuchi (NII) ICD2015-90 CPSY2015-103 |
End-to-end network latency has become an important issue for parallel application on large-scale High Performance Comput... [more] | ICD2015-90 CPSY2015-103 pp.105-110 |
| EMT, IEE-EMT | 2015-06-12 13:25 |
Tokyo | meeting room (1-5) of IEEJ | Design Study of FDTD/FIT Dataflow Machine for Wider Applications Hideki Kawaguchi (Muroran IT) EMT2015-5 |
For a purpose of practical use of microwave simulation technologies in industry applications, this paper presents a meth... [more] | EMT2015-5 pp.25-30 |
| IA | 2014-10-07 14:05 |
Osaka | Grand Front OSAKA Tower-B 10F | The necessity of global-scale R&D network infrastructure from the astronomical perspective Masafumi Oe (NAOJ) IA2014-27 |
This presentation describe that global-scale R&D network infrastructure become more important in the future from the ast... [more] | IA2014-27 pp.19-23 |
| CPSY, DC (Joint) |
2014-07-29 10:45 |
Niigata | Toki Messe, Niigata | Interconnect Design for Low Latency, High Topological Embeddability and Partitioning Capability by Supplementary Optical Circuit Switches Ryuta Kawano (Keio Univ.), Ikki Fujiwara (NII), Hiroki Matsutani, Hideharu Amano (Keio Univ.), Michihiro Koibuchi (NII) CPSY2014-20 |
This paper focuses on how to efficiently run multiple small parallel applications in a single High-performance computing... [more] | CPSY2014-20 pp.61-66 |
| CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] | 2014-03-16 10:50 |
Okinawa | HPC interconnect for high topological embeddability by supplementary optical circuit switches Ryuta Kawano (Keio Univ.), Ikki Fujiwara (NII), Hiroki Matsutani, Hideharu Amano (Keio Univ.), Michihiro Koibuchi (NII) CPSY2013-111 DC2013-98 |
Our goal is to run multiple parallel applications that have various communication patterns among participating processes... [more] | CPSY2013-111 DC2013-98 pp.253-258 |
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| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-28 08:30 |
Kanagawa | Hiyoshi Campus, Keio University | Design and implementation of high-level synthesis compiler for stream computation Ryo Ito, Hayato Suzuki, Ryotaro Chiba, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.) VLD2013-102 CPSY2013-73 RECONF2013-56 |
High-level synthesis (HLS) has been getting more and more important as FPGAs are more widely used for various applicati... [more] |
VLD2013-102 CPSY2013-73 RECONF2013-56 pp.1-6 |
| DC, CPSY (Joint) |
2012-08-03 14:30 |
Tottori | Torigin Bunka Kaikan | Rack Layout Optimization for Random Network Topology Ikki Fujiwara, Michihiro Koibuchi (NII) CPSY2012-25 |
As the scale of many-core parallel applications and supercomputer systems increases, the negative impact of communicatio... [more] | CPSY2012-25 pp.97-102 |
| VLD | 2010-03-12 14:35 |
Okinawa | Design and Implementation of an AMBA AHB Compliant Bus Architecture on FPGA Xuan-Tu Tran, Hai-Phong Phan, Van-Huan Tran, Quang-Vinh Tran, Ngoc-Binh Nguyen (Vietnam National Univ.) VLD2009-127 |
To meet the increasing demands of recent applications, systems-on-chips (SoCs) are more and more complex and one system ... [more] | VLD2009-127 pp.169-174 |
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