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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, HWS, ICD | 2024-03-01 14:00 |
Okinawa | (Primary: On-site, Secondary: Online) |
High-Level Synthesis Method for Python Considering Runtime Profiling Yusuke Suzuki, Makoto Ikeda (UTokyo)  VLD2023-127 HWS2023-87 ICD2023-116 |
With the increasing complexity of LSI design in recent years, high-level synthesis (HLS) technology has attracted attent... [more] | VLD2023-127 HWS2023-87 ICD2023-116 pp.145-150 |
| RECONF, VLD | 2024-01-30 13:20 |
Kanagawa | AIRBIC Meeting Room 1-4 (Primary: On-site, Secondary: Online) |
Reduction of Circuit Size by Optimizing Status Registers in Full Hardware RTOS-Based Systems Kei Mikami, Nagisa Ishiura (Kansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM) VLD2023-94 RECONF2023-97 |
This article presents a technique for handling increased number of tasks by reducing both circuit size and critical path... [more] | VLD2023-94 RECONF2023-97 pp.81-86 |
| RECONF, VLD | 2024-01-30 13:45 |
Kanagawa | AIRBIC Meeting Room 1-4 (Primary: On-site, Secondary: Online) |
Implementation of External Memory Access for Binary Synthesis Using General-Purpose High-Level Synthesizer Sho Kishimoto, Nagisa Ishiukra (Kwansei Gakuin Univ.) VLD2023-95 RECONF2023-98 |
In this article, we present a method for implementing external memory access within the context of binary synthesis util... [more] | VLD2023-95 RECONF2023-98 pp.87-92 |
| ICTSSL, CAS | 2024-01-25 11:00 |
Kanagawa | (Primary: On-site, Secondary: Online) |
Performance effect of memory access pattern for high-level synthesized sprite drawing hardware Yuka Otani, Akira Yamawaki (Kyutech) CAS2023-85 ICTSSL2023-38 |
We are developing a sprite drawing hardware suitable for high-level synthesis. Sprite drawing stores the sprite image in... [more] | CAS2023-85 ICTSSL2023-38 pp.17-22 |
| SIS | 2023-12-07 11:00 |
Aichi | Sakurayama Campus, Nagoya City University (Primary: On-site, Secondary: Online) |
Data Path Parallelization to Improve Performance of High-level Synthesized Sprite Drawing Hardware Yuka Otani, Akira Yamawaki (Kyutech) SIS2023-24 |
A mobile terminal architecture which can dynamically reconfigure the optimal hardware for each application can achieve h... [more] | SIS2023-24 pp.1-6 |
| SIS | 2023-12-07 11:20 |
Aichi | Sakurayama Campus, Nagoya City University (Primary: On-site, Secondary: Online) |
Development of a real-time non-photorealistic rendering system with a high-level synthesized pencil drawing style image conversion hardware Honoka Tani, Akira Yamawaki (Kyutech) SIS2023-25 |
We developed non-photorealistic rendering (NPR) libraries optimized for high-level synthesis (HLS) technology that autom... [more] | SIS2023-25 pp.7-12 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2023-11-16 14:10 |
Kumamoto | Civic Auditorium Sears Home Yume Hall (Primary: On-site, Secondary: Online) |
Hardware obfuscation method using Obfuscator-LLVM and Bambu Mikiya Ogura, Shuichi Ichikawa (Toyohashi Univ. Tech.) VLD2023-54 ICD2023-62 DC2023-61 RECONF2023-57 |
Hardware obfuscation serves as a countermeasure against hardware reverse engineering. Yamada et al. employed the OLLVM s... [more] | VLD2023-54 ICD2023-62 DC2023-61 RECONF2023-57 pp.125-130 |
| MSS, CAS, SIP, VLD | 2023-07-06 09:30 |
Hokkaido | (Primary: On-site, Secondary: Online) |
Performance Improvement by Integrating Former and Latter Processes of Pencil Drawing Style Image Conversion on High-Level Synthesized Hardware. Honoka Tani, Akira Yamawaki (Kyutech) CAS2023-1 VLD2023-1 SIP2023-17 MSS2023-1 |
We are developing hardware to realize a high-performance and low-power embedded image processing device using high-level... [more] | CAS2023-1 VLD2023-1 SIP2023-17 MSS2023-1 pp.1-5 |
| MSS, CAS, SIP, VLD | 2023-07-06 10:10 |
Hokkaido | (Primary: On-site, Secondary: Online) |
Performance Improvement by Memory access and Process-level Pipelining for High-level Synthesized Sprite Drawing Hardware Yuka Otani, Akira Yamawaki (Kyutech) CAS2023-3 VLD2023-3 SIP2023-19 MSS2023-3 |
A mobile terminal with hardware reconfigurability can achieve higher performance and lower power consumption by performi... [more] | CAS2023-3 VLD2023-3 SIP2023-19 MSS2023-3 pp.10-15 |
| RECONF | 2023-06-08 16:00 |
Kochi | Eikokuji Campus, Kochi University of Technology (Primary: On-site, Secondary: Online) |
Parallelization of Prim's Algorithm Using FPGA and Its Performance Evaluation Noritsune O, Kenji Kanazawa, Moritoshi Yasunaga (Univ. of Tsukuba) RECONF2023-3 |
A subgraph of an undirected graph G that is connected and contains no closed paths is called a tree, a global tree is a ... [more] | RECONF2023-3 pp.13-16 |
| HWS, VLD | 2023-03-02 11:50 |
Okinawa | (Primary: On-site, Secondary: Online) |
Automatic Synthesis of Decoupled Data Orchestration in High-Level Synthesis Masayuki Usui, Shinya Takamaeda (UTokyo) VLD2022-90 HWS2022-61 |
We automatically decouple data orchestration mechanisms in explicit data orchestration to facilitate accelerator design.... [more] | VLD2022-90 HWS2022-61 pp.103-108 |
| CAS, CS | 2023-03-01 14:50 |
Fukuoka | Kitakyushu International Conference Center (Primary: On-site, Secondary: Online) |
Memory access optimization for former process of pencil drawing style image conversion in High-level Synthesis Honoka Tani, Akira Yamawaki (Kyutech) CAS2022-105 CS2022-82 |
To effectively use high-level synthesis, which automatically converts software to hardware, it is necessary to create so... [more] | CAS2022-105 CS2022-82 pp.53-58 |
| RECONF | 2022-06-07 13:50 |
Ibaraki | CCS, Univ. of Tsukuba (Primary: On-site, Secondary: Online) |
Hardware implementation of the protocol for ROS2 and robot modules without CPU Daiki Matsunaga, Tomoya Shoji, Shozo Takeoka (AXE) RECONF2022-3 |
ROS2 is a set of software libraries and tools for robot applications. It is widely used in robot development. A ROS2 rob... [more] | RECONF2022-3 pp.13-19 |
| VLD, HWS [detail] | 2022-03-07 10:00 |
Online | Online | A Heuristic Scheduling Algorithm with Variable-Cycle Approximate Operations in High-Level Synthesis Koyu Ohata, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2021-78 HWS2021-55 |
This paper studies a scheduling algorithm for high-level synthesis that takes into account the difference in delay betwe... [more] | VLD2021-78 HWS2021-55 pp.13-18 |
| IE, ITS, ITE-AIT, ITE-ME, ITE-MMS [detail] | 2022-02-22 14:25 |
Online | Online | Development of a Real Camera System with High-Level Synthesis Hardware of Median-Based Dynamic Background Subtraction Kohei Shinyamada, Akira Yamawaki (Kyutech) ITS2021-61 IE2021-70 |
In this study, we developed a median-based dynamic background subtraction image processing system equipped with a real c... [more] | ITS2021-61 IE2021-70 pp.214-218 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-24 10:20 |
Online | Online | Full Hardware Implementation of RTOS-Based Systems Using General-Purpose High-Level Synthesizer Takuya Ando, Yugo Ishii, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO) VLD2021-51 CPSY2021-20 RECONF2021-59 |
This article proposes a method for implementing a whole RTOS-based system as hardware using general-purpose high-level s... [more] | VLD2021-51 CPSY2021-20 RECONF2021-59 pp.13-18 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-24 10:45 |
Online | Online | Design of Inter-Task Communication Modules for Full Hardware Implementation of RTOS-Based Systems Yukino Shinohara, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2021-52 CPSY2021-21 RECONF2021-60 |
This paper presents hardware implementation of inter-task communication functions of RTOS, in the scheme where all the t... [more] | VLD2021-52 CPSY2021-21 RECONF2021-60 pp.19-24 |
| HWS, VLD [detail] | 2021-03-03 14:55 |
Online | Online | Aggregating Service Functions in Full Hardware Implementation of RTOS-Based Systems Iori Muguruma, Nagisa Ishiura, Takuya Ando (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO) VLD2020-75 HWS2020-50 |
This article presents a revised architecture for full-hardware implementation of RTOS-based systems. In the previous m... [more] |
VLD2020-75 HWS2020-50 pp.38-43 |
| HWS, VLD [detail] | 2021-03-04 09:55 |
Online | Online | High-level synthesis of approximate circuits with two-level accuracies Kenta Shirane, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama (Ritumeikan Univ.) VLD2020-80 HWS2020-55 |
This paper studies high-level synthesis (HLS) of approximate computing circuits with multiple accuracy levels. This work... [more] | VLD2020-80 HWS2020-55 pp.67-72 |
| HWS, VLD [detail] | 2021-03-04 14:55 |
Online | Online | FPGA Implementation of Lightweight Cipher Chaskey through High-Level Synthesis and its Evaluation of Side-Channel Attack Resistance Saya Inagaki, Mingyu Yang (Tokyo Tech), Yang Li, Kazuo Sakiyama (UEC), Yuko Hara (Tokyo Tech) VLD2020-86 HWS2020-61 |
(To be available after the conference date) [more] | VLD2020-86 HWS2020-61 pp.102-107 |
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