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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 11 of 11  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM 2014-06-19
09:30
Aichi VBL, Nagoya Univ. Process Design of High-k/Ge Gate Stack for Improving Thermal Stability and Interface Properties in Sub-1-nm Regime
Ryohei Asahara, Takuji Hosoi, Takayoshi Shimura, Heiji Watanabe (Osaka Univ.) SDM2014-43
Suppression of GeOx formation and Ge diffusion into high-k layer is important to develop sub-1-nm EOT metal/high-k gate ... [more] SDM2014-43
pp.1-5
SDM 2013-06-18
11:15
Tokyo Kikai-Shinko-Kaikan Bldg. Impact of metal gate electrodes on electrical properties of InGaAs MOS gate stacks
Chih-Yu Chang, Masafumi Yokoyama, Sang-Hyeon Kim (Univ. of Tokyo), Osamu Ichikawa, Takenori Osada, Masahiko Hata (Sumitomo Chemical), Mitsuru Takenaka, Shinichi Takagi (Univ. of Tokyo) SDM2013-50
Electrical properties of Al2O3 and HfO2/InGaAs metal-oxide-semiconductor (MOS) capacitors with Al, Au and Pd gate electr... [more] SDM2013-50
pp.33-37
SDM 2012-06-21
11:55
Aichi VBL, Nagoya Univ. Oxygen-induced high-k dielectric degradation in TiN/Hf-based high-k gate stacks
Takuji Hosoi, Yuki Odake, Hiroaki Arimura, Keisuke Chikaraishi, Naomu Kitano, Takayoshi Shimura, Heiji Watanabe (Osaka Univ.) SDM2012-51
Effective work function control and equivalent oxide thickness (EOT) scaling are the major concerns for implementing met... [more] SDM2012-51
pp.43-46
SDM 2011-07-04
15:40
Aichi VBL, Nagoya Univ. Hf and La upward diffusion into TiN electrode in TiN/HfLaSiO/SiO2 gate stacks induced by high-temperature annealing and its suppression with MIPS structure
Yuki Odake, Hiroaki Arimura, Masayuki Saeki, Keisuke Chikaraishi, Naomu Kitano, Takuji Hosoi, Takayoshi Shimura, Heiji Watanabe (Osaka Univ.) SDM2011-65
We investigated Hf and La upward diffusion in TiN/HfLaSiO/SiO2 gate stacks by means of electrical characterization and X... [more] SDM2011-65
pp.87-92
SDM 2010-11-11
14:40
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Comprehensive understanding of oxygen vacancy induced effective work function modulation in high-k/metal gate stacks
Takuji Hosoi, Masayuki Saeki, Yuki Kita, Yudai Oku, Hiroaki Arimura, Naomu Kitano (Osaka Univ.), Kenji Shiraishi, Keisaku Yamada (Univ. Tsukuba), Takayoshi Shimura, Heiji Watanabe (Osaka Univ.) SDM2010-175
Effective work function of p-type gate electrodes on Hf-based high-k dielectrics is known to decrease after high tempera... [more] SDM2010-175
pp.23-28
SDM 2010-06-22
13:45
Tokyo An401・402 Inst. Indus. Sci., The Univ. of Tokyo High Temperature Rapid Thermal Annealing of Rare-Earth Oxides Dielectrics for Highly Scaled Gate Stack of EOT=0.5 nm
Daisuke Kitayama, Tomotsune Koyanagi, Kuniyuki Kakushima, Parhat Ahmet, Kazuo Tsutsui, Akira Nishiyama, Nobuyuki Sugii, Kenji Natori, Takeo Hattori, Hiroshi Iwai (Tokyo Inst. of Tech.) SDM2010-41
A direct contact of high-k/Si substrate (without SiO<sub>2</sub> interfacial layer structure) is required for achieving ... [more] SDM2010-41
pp.43-48
SDM 2009-06-19
14:10
Tokyo An401・402 Inst. Indus. Sci., The Univ. of Tokyo Electrical Characterization of High-k Gate Dielectrics on Ge with HfGeN and GeO2 Interlayers -- Formation of Insulator on Ge Substrate --
Hiroshi Nakashima, Kana Hirayama, Haigui Yang, Dong Wang (Kyushu Univ.) SDM2009-35
We are searching MIS structure with good interface and insulating properties for high mobility Ge channel. Our approach... [more] SDM2009-35
pp.51-56
SDM 2009-06-19
15:10
Tokyo An401・402 Inst. Indus. Sci., The Univ. of Tokyo Investigation of Al2O3 Diffusion Annealing Process for Low Vt pMISFET with Al2O3-Capped HfO2 Dielectrics
Tetsu Morooka, Takeo Matsuki, Nobuyuki Mise, Satoshi Kamiyama, Toshihide Nabatame, Takahisa Eimori, Yasuo Nara, Jiro Yugami, Kazuto Ikeda, Yuzuru Ohji (Selete) SDM2009-38
We have systematically studied the effect of post deposition annealing (PDA) for Al2O3-capped HfO2 on flatband voltage (... [more] SDM2009-38
pp.67-70
SDM 2008-06-10
09:55
Tokyo An401・402, Inst. Indus. Sci., The Univ. of Tokyo Gate Dielectrics Interface Control for III-V MISFET
Tetsuji Yasuda, Noriyuki Miyata (AIST), Akihiro Ohtake (NIMS) SDM2008-49
Introduction of III-V semiconductors to the n channel of CMOS devices is one of the options to sustain performance impro... [more] SDM2008-49
pp.41-46
SDM 2007-06-08
12:45
Hiroshima Hiroshima Univ. ( Faculty Club) Annealing atmosphere dependence of effective work function of metal gates on LaAlO3 gate dielectrics.
Masamichi Suzuki, Yoshinori Tsuchiya, Masato Koyama (Toshiba) SDM2007-45
The effective work functions (Φeff ) of various metals on LaAlO3 were systematically investigated. Contrary to the case ... [more] SDM2007-45
pp.75-80
ICD, SDM 2005-08-19
11:10
Hokkaido HAKODATE KOKUSAI HOTEL Improvement of threshold voltage asymmetry by Al compositional mudulation and partially silicided gate electrode for Hf-based high-k CMOSFETs
Masaru Kadoshima, Arito Ogawa, Masashi Takahashi (MIRAI-ASET), Hiroyuki Ota (MIRAI-ASRC, AIST), Nobuyuki Mise, Kunihiko Iwamoto (MIRAI-ASET), Shinji Migita (MIRAI-ASRC, AIST), Hideaki Fujiwara, Hideki Satake, Toshihide Nabatame (MIRAI-ASET), Akira Toriumi (MIRAI-ASRC, AIST, The Univ. of Tokyo)
Threshold voltage (Vth) tuning by engineering Fermi-level pinning (FLP) on HfAlOx(N) dielectrics is demonstrated for CMO... [more] SDM2005-148 ICD2005-87
pp.31-36
 Results 1 - 11 of 11  /   
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