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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] |
2016-01-20 16:35 |
Kanagawa |
Hiyoshi Campus, Keio University |
A performance evaluation of PEACH3 Takahiro Kaneda, Chiharu Tsuruta (Keio Univ), Toshihiro Hanawa (UTokyo), Hideharu Amano (Keio Univ) VLD2015-96 CPSY2015-128 RECONF2015-78 |
A recent rapid increase of GPU performance makes GPGPU (General Purpose Computation using on GPUs) a mainstream of high ... [more] |
VLD2015-96 CPSY2015-128 RECONF2015-78 pp.155-160 |
ICD, SDM |
2014-08-04 10:50 |
Hokkaido |
Hokkaido Univ., Multimedia Education Bldg. |
A 28nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor with 2GHz Cores and Low-Power 1GHz Cores Mitsuhiko Igarashi, Toshifumi Uemura, Ryo Mori, Hiroshi Kishibe, Masaaki Taniguchi, Kohei Wakahara, Toshiharu Saito, Masaki Fujigaya, Kazuki Fukuoka, Koji Nii, Takeshi Kataoka, Toshihiro Hattori (Renesas Electronics) SDM2014-64 ICD2014-33 |
This paper presents power management and low power techniques of our heterogeneous quad/octa-core mobile application pro... [more] |
SDM2014-64 ICD2014-33 pp.11-16 |
RECONF |
2012-05-29 17:35 |
Okinawa |
Tiruru (Naha Okinawa, Japan) |
Development of Application for Heterogeneous Multi-Core Processor Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano (Keio Univ.), Ryuichi Sakamoto, Mitaro Namiki (Tkyo Univ. of Agri. and Tech.) RECONF2012-16 |
This paper describes the application development on a heterogeneous multi-core processor that consists of a CPU and acce... [more] |
RECONF2012-16 pp.89-94 |
ICD, IE, SIP, IPSJ-SLDM [detail] |
2011-10-25 13:30 |
Miyagi |
Ichinobo(Sendai) |
FPGA Platform for Heterogeneous Multicore Processors with MIMD-ALU-array-type Dynamically Reconfigurable Accelerators Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) SIP2011-73 ICD2011-76 IE2011-72 |
Heterogeneous multi-core architectures with CPUs and accelerators attract many attentions since they can achieve energy-... [more] |
SIP2011-73 ICD2011-76 IE2011-72 pp.73-76 |
VLD |
2010-09-27 14:25 |
Kyoto |
Kyoto Institute of Technology |
Accelerator-Centric Task Allocation Based on Algorithm Transformation for Heterogeneous Multicore Processors Masanori Hariyama, Hasitha Muthumala Waidyasooriya, Michitaka Kameyama (Tohoku Univ.) VLD2010-43 |
Heterogeneous multi-core processors are attracted by the media processing applications
due to their capability of drawi... [more] |
VLD2010-43 pp.7-12 |
ICD, IPSJ-ARC, IPSJ-EMB |
2009-01-14 11:15 |
Osaka |
Shoushin Kaikan |
Performance Evaluation of Parallelizing Compiler Cooperated Heterogeneous Multicore Architecture Using Media Applications Teruo Kamiyama, Yasutaka Wada, Akihiro Hayashi, Masayoshi Mase, Hirofumi Nakano, Takeshi Watanabe, Keiji Kimura, Hironori Kasahara (Waseda Univ.) |
This paper describes a heterogeneous multicore architecture having accelerator cores in addition to general purpose core... [more] |
ICD2008-140 pp.63-68 |
ICD, IPSJ-ARC |
2008-05-14 09:30 |
Tokyo |
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Design and Evaluation of a Heterogeneous Multicore SoC with 9 CPUs and 2 Matrix Processors Masami Nakajima, Koichi Ishimi, Naoto Okumura, Norio Masui, Osamu Yamamoto, Hiroyuki Kondo (Renesas) ICD2008-26 |
A multicore SoC has been developed for various applications (recognition, inference, measurement, control and security) ... [more] |
ICD2008-26 pp.45-50 |
ICD, SDM |
2007-08-23 08:30 |
Hokkaido |
Kitami Institute of Technology |
Development of a Multi-Core SoC with 9 CPUs and 2 Matrix Processors Masami Nakajima, Koichi Ishimi, Hayato Fujiwara, Kazuya Ishida, Naoto Okumura, Norio Masui, Hiroyuki Kondo (Renesas) SDM2007-141 ICD2007-69 |
A multi-core SoC for multi-application (recognition, inference, measurement, control, and security) is developed. The co... [more] |
SDM2007-141 ICD2007-69 pp.1-4 |
ICD, SDM |
2007-08-23 09:20 |
Hokkaido |
Kitami Institute of Technology |
Evaluation of Heterogeneous Multicore Architecture with AAC-LC Stereo Encoding Hiroaki Shikano (Hitachi/./Waseda Univ.), Masaki Ito, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Masafumi Onouchi, Kunio Uchiyama (Hitachi), Toshihiko Odaka (Hitachi/./Waseda Univ.), Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta (Renesas Technology), Yasutaka Wada, Keiji Kimura, Hironori Kasahara (Waseda Univ.) SDM2007-143 ICD2007-71 |
This paper describes a heterogeneous multi-core processor (HMCP) architecture which integrates general purpose processor... [more] |
SDM2007-143 ICD2007-71 pp.11-16 |
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