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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 10 of 10  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
IE, ICD, VLD, IPSJ-SLDM [detail] 2014-10-02
14:15		 Miyagi   Hierarchical GALS system based on ring segmented bus architecture
Masafumi Kondo (Kawasaki Univ. of Medical Welfare), Tomoyuki Yokogawa, Yoichiro Sato, Kazutami Arimoto (Okayama Prefectural Univ.) VLD2014-63 ICD2014-56 IE2014-42		 A ring segmented bus (RSB) which connects the divided annular bus dynamically has been proposed as an asynchronous bus a... [more] VLD2014-63 ICD2014-56 IE2014-42
pp.19-24
CAS, SIP, MSS, VLD, SIS [detail] 2014-07-11
15:10		 Hokkaido Hokkaido University A distributed asynchronous arbiter for ring segmented bus type GALS systems
Yoshiki Odagiri, Masaki Akari (Okayama Prefectural Univ.), Masafumi Kondo (Kawasaki Univ. of Medical Welfare), Tomoyuki Yokogawa, Yoichiro Sato, Kazutami Arimoto (Okayama Prefectural Univ.) CAS2014-44 VLD2014-53 SIP2014-65 MSS2014-44 SIS2014-44		 A ring segmented bus (RSB) which connects the divided annular bus dynamically has been proposed for GALS systems. Howeve... [more] CAS2014-44 VLD2014-53 SIP2014-65 MSS2014-44 SIS2014-44
pp.237-242
CS, CAS, SIP 2014-03-06
13:25		 Osaka Osaka City University Media Center High-speed Petri Net Simulation Using Matrix Compression and GPGPU
Takashi Kawamura, Yoichiro Sato, Tomoyuki Yokogawa (Okayama Prefectural Univ.), Masafumi Kondo (Kawasaki Univ. of Medical Welfare), Kazutami Arimoto (Okayama Prefectural Univ.) CAS2013-106 SIP2013-152 CS2013-119		 We proposed a method of evaluating performance of large scale digital systems by modeling with the STPN and executing pe... [more] CAS2013-106 SIP2013-152 CS2013-119
pp.91-96
CAS, MSS 2011-11-17
14:15		 Yamaguchi Univ. of Yamaguchi A Method of Generating Incidence Matrices for High-Speed Petri Net Simulation
Masafumi Kondo, Yusuke Koyoshi, Tomoyuki Yokogawa, Yoichiro Sato (Okayama Prefectural Univ) CAS2011-67 MSS2011-36		 A high-speed method of evaluating performance of large scale digital systems by combination with analytical approaches ... [more] CAS2011-67 MSS2011-36
pp.19-24
DC, CPSY 2011-04-12
13:50		 Tokyo   A Case Study on Dependable Network-on-Chip Platform for Automotive Applications
Chammika Mannakkara, Daihan Wang, Vijay Holimath, Tomohiro Yoneda (NII) CPSY2011-3 DC2011-3		 This report presents our first trial to apply a Network-on-Chip (NoC)
architecture to a gasoline engine control, one of... [more]		 CPSY2011-3 DC2011-3
pp.11-16
RECONF 2010-05-14
11:20		 Nagasaki   GALS Design for Scalable Array Processors Operating on Multiple FPGAs
Wang Luzhou, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.) RECONF2010-13		 So far we have proposed systolic computational-memory (SCM) architecture for high-performance and scalable computation b... [more] RECONF2010-13
pp.69-74
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2009-12-02
10:40		 Kochi Kochi City Culture-Plaza Implementation of Asynchronous Bus for GALS System
Takehiro Hori, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.) CPM2009-135 ICD2009-64		 Although asynchronous circuit can solve problems of power consumption, speed, noise, and clockskew, the transmission is ... [more] CPM2009-135 ICD2009-64
pp.7-12
VLD 2009-03-12
14:50		 Okinawa   A ring segmented bus architrcture for Globally Asynchronous Locally Synchronous System
Masafumi Kondo, Yoichiro Sato (Okayama Prefectural Univ), Kazuyuki Tashiro (FUJITSU TEN), Tomoyuki Yokogawa, Michiyoshi Hayase (Okayama Prefectural Univ) VLD2008-149		 Recently, most digital systems are designed as GALS (Globally Asynchronous Locally Synchronous) systems.
Several archit... [more]		 VLD2008-149
pp.135-140
VLD 2009-03-12
15:15		 Okinawa   Formal verification of GALS system designs using UPPAAL
Kazuaki Kirita, Tomoyuki Yokogawa, Hisashi Miyazaki, Yoichiro Sato, Michiyoshi Hayase (Okayama Pref. Univ.) VLD2008-150		 To design GALS (Globally Asynchronous Locally Synchronous) systems,
it is necessary to verify the correctness of behavi... [more]		 VLD2008-150
pp.141-146
VLD, CPSY, RECONF, IPSJ-SLDM 2009-01-30
14:45		 Kanagawa   Implementation of Asynchronous Bus for GALS System
Takehiro Hori, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.) VLD2008-120 CPSY2008-82 RECONF2008-84		 Although asynchronous circuit can solve problems of power consumption, speed, noise, and clockskew, the transmission is ... [more] VLD2008-120 CPSY2008-82 RECONF2008-84
pp.171-176
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