Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
RECONF, VLD |
2024-01-29 10:55 |
Kanagawa |
AIRBIC Meeting Room 1-4 (Primary: On-site, Secondary: Online) |
Suppression of output bit width growth in AFE stochastic computing units Daiki Seto, Naoki Fujieda (Aichi Inst. Tech.) VLD2023-81 RECONF2023-84 |
Stochastic Computing (SC) is expected to be applied to fields such as image processing and machine learning. Amplitude a... [more] |
VLD2023-81 RECONF2023-84 pp.7-12 |
RECONF, VLD |
2024-01-29 15:55 |
Kanagawa |
AIRBIC Meeting Room 1-4 (Primary: On-site, Secondary: Online) |
VLD2023-88 RECONF2023-91 |
Quantum computer simulation is indispensable for quantum algorithm research since the results of real
quantum computers... [more] |
VLD2023-88 RECONF2023-91 pp.47-52 |
SANE |
2023-11-13 13:05 |
Chiba |
Chiba Univ. (Nishi-Chiba Campus) (Primary: On-site, Secondary: Online) |
Board design of digital chirp generator using FPGA Yoshiaki Saito, Kazuteru Namba, Josaphat Tetuko Sri Sumantyo (Chiba Univ.) SANE2023-52 |
Remote sensing, which enables observation of an object without touching it, has been widely used for earth observation i... [more] |
SANE2023-52 pp.28-33 |
SeMI, RCS, RCC, NS, SR (Joint) |
2023-07-14 14:00 |
Osaka |
Osaka University Nakanoshima Center + Online (Primary: On-site, Secondary: Online) |
FPGA implementation of ML-compensation for SVD-MIMO weight matrices Kiminobu Makino, Takayuki Nakagawa (NHK) RCS2023-99 |
This paper proposes a computation reduction method of machine learning-based compensation of transmission (Tx) weight ma... [more] |
RCS2023-99 pp.103-108 |
SANE |
2023-06-30 13:00 |
Kanagawa |
JAXA Sagamihara Campus (Primary: On-site, Secondary: Online) |
Study of implementation of on-board SAR with FPGA Hiroai Asami (Mitsubishi Electric Corp.) SANE2023-18 |
We have studied to implement the image reconstruction processing of the synthetic aperture radar on the FPGA and to proc... [more] |
SANE2023-18 pp.17-20 |
IPSJ-SLDM, RECONF, VLD [detail] |
2023-01-23 10:30 |
Kanagawa |
Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
Multi-FPGA design environment using Cyberworkbench, a high-level synthesis tool Hiroaki Suzuki (Keio Univ), Wataru Takahashi (NEC), Kazutoshi Wakabayashi (Tokyo Univ), Hideharu Amano (Keio Univ) VLD2022-56 RECONF2022-79 |
Multi-FPGA systems, in which multiple FPGA boards are directly connected via high-speed serial links, are attracting att... [more] |
VLD2022-56 RECONF2022-79 pp.1-6 |
IPSJ-SLDM, RECONF, VLD [detail] |
2023-01-24 10:30 |
Kanagawa |
Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
Measurement results of soft error tolerance of LPDDR4 SDRAM and GDDR5 SDRAM Motoki Kamibayashi, Kazutoshi Kobayashi (Kyoto Inst. of Tech.), Masanori Hashimoto (Kyoto Univ.) VLD2022-65 RECONF2022-88 |
In recent years, as the memory capacity of computer systems has increased,the reliability of the system has decreased.So... [more] |
VLD2022-65 RECONF2022-88 pp.34-39 |
IPSJ-SLDM, RECONF, VLD [detail] |
2023-01-24 13:30 |
Kanagawa |
Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
Implementing a quantum computer simulator Qulacs on FPGAs Hideharu Amano, Wei Kaijie (Keio Univ.), Takefumi Miyoshi (Wasalab.), Yoshiki Yamaguchi, Ryohei Niwase (U.niv. of Tsukuba) VLD2022-72 RECONF2022-95 |
Quantum computer simulation is indispensable for quantum algorithm research since the results of real
quantum computers... [more] |
VLD2022-72 RECONF2022-95 pp.74-79 |
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] |
2022-11-30 16:40 |
Kumamoto |
(Primary: On-site, Secondary: Online) |
Evaluation of Model Quantization Method on Vitis-AI for Mitigating Adversarial Examples Yuta Fukuda, Kota Yoshida, Takeshi Fujino (Ritsumeikan Univ.) VLD2022-51 ICD2022-68 DC2022-67 RECONF2022-74 |
Adversarial examples (AEs) are security threats in deep neural networks (DNNs). One of the countermeasures is adversaria... [more] |
VLD2022-51 ICD2022-68 DC2022-67 RECONF2022-74 pp.182-187 |
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] |
2022-11-30 16:15 |
Kumamoto |
(Primary: On-site, Secondary: Online) |
FPGA Implementation of Learned Image Compression Heming Sun (Waseda U), Qingyang Yi (UTokyo), Jiro Katto (Waseda U), Masahiro Fujita (UTokyo) VLD2022-53 ICD2022-70 DC2022-69 RECONF2022-76 |
Learned image compression (LIC) has reached a superior coding gain than traditional hand-crafted standards such as JPEG ... [more] |
VLD2022-53 ICD2022-70 DC2022-69 RECONF2022-76 pp.194-199 |
SAT, RCS (Joint) |
2022-08-25 14:45 |
Hokkaido |
(Primary: On-site, Secondary: Online) |
[Invited Lecture]
R&D Trends in Onboard Paylaod toward NTN Shigenori Tani, Michiya Hayama, Futaba Ejima, Hideki Ishihara, Hiroyuki Tanaka (Mitsubishi Electric), Johta Awano, Masanobu Yajima (JAXA) SAT2022-33 RCS2022-108 |
Satellite communications have traditionally been a relatively closed network, but with the standardization of NTNs, a wi... [more] |
SAT2022-33 RCS2022-108 pp.25-29(SAT), pp.61-65(RCS) |
SIS, IPSJ-AVM |
2022-06-09 13:00 |
Fukuoka |
KIT(Wakamatsu Campus) (Primary: On-site, Secondary: Online) |
Hardware Implementation of Annealing Machine using Chaotic Boltzmann Machine Kanta Yoshioka (Kyutech), Ichiro Kawashima, Hakaru Tamukoh (Kyutech/Neumorph Center) SIS2022-1 |
With the end of Moore's law, annealing quantum computers that can solve various combinatorial optimization problems are ... [more] |
SIS2022-1 pp.1-6 |
RECONF |
2022-06-08 09:45 |
Ibaraki |
CCS, Univ. of Tsukuba (Primary: On-site, Secondary: Online) |
Consideration of speeding up AI inference processing by cooperative operation of hardware and software Tomoya Kawakami, Chikako Nakanishi (OIT) RECONF2022-14 |
When cooperative processing of AI inference processing between software and hardware, it is difficult to analyze network... [more] |
RECONF2022-14 pp.57-62 |
RECONF |
2022-06-08 14:00 |
Ibaraki |
CCS, Univ. of Tsukuba (Primary: On-site, Secondary: Online) |
RECONF2022-19 |
Data has increased dramatically in recent years, and it is important to speed up parallel data processing using multiple... [more] |
RECONF2022-19 p.86 |
NS, IN (Joint) |
2022-03-11 11:00 |
Online |
Online |
Sustainable realtime information sharing mobile networks Akira Tanaka (NIT, Tokyo College), Mitsuru Maruyama (KAIT), Shigeo Urushidani (NII), Tsujii Toshiaki (OPU) NS2021-147 |
We have designed real-time information sharing communication platform on many multihop networks composed of familiar dev... [more] |
NS2021-147 pp.146-151 |
RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] |
2022-01-24 11:25 |
Online |
Online |
FPGA Implementation of Scalable Fully Coupled Annealing Processing Sysytem by Using Multi-chip Operation Kaoru Yamamoto, Takayuki Kawahara (TUS) VLD2021-53 CPSY2021-22 RECONF2021-61 |
Annealing machines can be classified into sparsely coupled types and fully coupled types. The fully coupled type has the... [more] |
VLD2021-53 CPSY2021-22 RECONF2021-61 pp.25-30 |
NLP |
2021-12-18 10:40 |
Oita |
J:COM Horuto Hall OITA |
Optimization and FAGA based implementation of digital spike maps Tomoki Harada, Toshimichi Saito (HU) NLP2021-58 |
This paper studies optimization and
FPGA based implementation of digital spike maps.
First, the dynamics of spike-tra... [more] |
NLP2021-58 pp.67-71 |
SANE |
2021-12-16 14:55 |
Chiba |
Chiba University (Primary: On-site, Secondary: Online) |
Comparison of HLS and IP core for CP-SAR images processing onboard UAV Yuta Tanaka, Takumi Aoyama, Kazuteru Namba, Josaphat Tetuko Sri Sumantyo (Chiba Univ) SANE2021-76 |
(To be available after the conference date) [more] |
SANE2021-76 pp.75-78 |
VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2021-12-01 09:20 |
Online |
Online |
Block Sparse MLP-based Vision DNN Accelerators on Embedded FPGAs Akira Jinguji, Hiroki Nakahara (Tokyo Tech) VLD2021-21 ICD2021-31 DC2021-27 RECONF2021-29 |
Since the advent of Vision Transformer, a deep learning model for image recognition without Convolution, MLP-based model... [more] |
VLD2021-21 ICD2021-31 DC2021-27 RECONF2021-29 pp.25-30 |
VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2021-12-02 09:20 |
Online |
Online |
The Implementation of a Hybrid Router with Dynamic Communication Priority Changes on a Multi-FPGA System Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano (Keio Univ.) VLD2021-36 ICD2021-46 DC2021-42 RECONF2021-44 |
We are currently developing a multi-FPGA system, Flow-in-Cloud (FiC) system. FiC directly interconnects multiple middle-... [more] |
VLD2021-36 ICD2021-46 DC2021-42 RECONF2021-44 pp.111-116 |