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 Results 1 - 14 of 14  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
LOIS, SITE, ISEC 2023-11-09
13:05		 Hiroshima Satellite Campus Hiroshima
(Primary: On-site, Secondary: Online)		 An Optimization Method for Share Reconstruction in (k,n)-Threshold Secret Sharing Scheme Using Exclusive-OR
Shogo Naganuma, Yutaro Taki, Shigeru Fujita (CIT) ISEC2023-56 SITE2023-50 LOIS2023-14		 We propose a method to reduce the computational complexity of generating extended shares and regenerating lost shares in... [more] ISEC2023-56 SITE2023-50 LOIS2023-14
pp.10-17
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-27
14:05		 Kagoshima   Improved via programmable structured ASIC VPEX3S -- Improvement of basic logic element to improve operation speed --
Taku Otani, Ryohei Hori (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.) VLD2013-70 DC2013-36		 We have been studying via programmable structured ASIC architecture “VPEX3(Via Programmable Logic using Exclusive-OR Arr... [more] VLD2013-70 DC2013-36
pp.75-80
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-27
14:30		 Kagoshima   New Via Programmable Architecture VPEX4 (1) -- Development of new logic element for improvement of routability and power consumption --
Ryohei Hori, Taku Otani, Tatsuro Hitomi, Shota Ueguchi (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.) VLD2013-71 DC2013-37		 The Non-Recruring Engineering (NRE) cost of LSI is increasing drastically with the advances in LSI process and manufactu... [more] VLD2013-71 DC2013-37
pp.81-86
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-27
14:55		 Kagoshima   Evaluation of Via Programmable Device named VPEX using benchmark circuits
Shota Ueguchi, Ryohei Hori, Taku Otani (Ritsumeikan Univ.), Masaya Yoshikawa (Meijyo Univ.), Takeshi Fujino (Ritsumeikan Univ.) VLD2013-72 DC2013-38		 Non-Recurring engineering cost including photo-mask cost increases with LSI process minimization. We have been studied v... [more] VLD2013-72 DC2013-38
pp.87-92
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2012-11-28
09:50		 Fukuoka Centennial Hall Kyushu University School of Medicine Performance evaluation of Via Programmable Logic VPEX using P&R tool
Taku Otani, Ryohei Hori, Taisuke Ueoka (Ritsumeikan Univ), Masaya Yoshikawa (Meijo Univ), Takeshi Fujino (Ritsumeikan Univ) VLD2012-90 DC2012-56		 We have been studying via programmable structured ASIC architecture “VPEX” which can realize arbitrary logic by customiz... [more] VLD2012-90 DC2012-56
pp.177-182
IT 2012-09-28
08:45		 Gunma Kusatsu Seminar House Optimization of Exclusive-OR Operations in Parallel Bit Encoding and Parallel Bit Decoding for Hamming Code
Reiya Ooshima, Ken-ichi Iwata (Univ. of Fukui) IT2012-35		 The paper consider an optimization of the amount of exclusive-or operations in the parallel bit encoding or the parallel... [more] IT2012-35
pp.25-30
VLD 2012-03-06
10:35		 Oita B-con Plaza Performance evaluation and Improvement of Via Programmable Logic VPEX
Taku Otani, Ryohei Hori, Tatsuya Kitamori, Taisuke Ueoka (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.) VLD2011-121		 We have been studying via programmable structured ASIC architecture “VPEX” which can realize arbitrary logic by customiz... [more] VLD2011-121
pp.7-12
VLD 2011-03-04
15:30		 Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center Performance Evaluation of Via Programmable ASIC Architecture VPEX3
Taisuke Ueoka, Tatsuya Kitamori, Ryohei Hori (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.) VLD2010-146		 We have been studying via programmable ASIC architecture “VPEX” whose logic element (LE) consists of complex-gate type E... [more] VLD2010-146
pp.177-182
VLD 2010-03-11
10:25		 Okinawa   Examination of the best basic logic gate architecture for Via programmable logic device
Ryohei Hori, Yuuichi Kokushou, Tomohiro Nishimoto, Shouta Yamada, Naoyuki Yoshida, Naoki Matsumoto, Takeshi Fujino (Ritsumei Univ.), Masaya Yoshikawa (Meijo Univ.) VLD2009-108		 The structured ASIC on which the logic can be customized with a few mask layers, have been studied in order to reduce in... [more] VLD2009-108
pp.55-60
VLD 2010-03-11
10:50		 Okinawa   Wiring delay of Logic Element used in Via programmable logic device VPEX
Tomohiro Nishimoto, Tatsuya Kitamori, Yuuichi Kokushou, Shouta Yamada (Ritsumeikan Univ), Masaya Yoshikawa (Meijou Univ), Takeshi Fujino (Ritsumeikan Univ) VLD2009-109		 We have been studied the via-programmable-device VPEX (Via Programmable logic using EXclusive or array) whose logic elem... [more] VLD2009-109
pp.61-66
VLD 2009-03-12
09:15		 Okinawa   Chip evaluation and implimentation of DES encryption using via-programmable-device VPEX
Masahide Kawarasaki, Tomohiro Nishimoto, Yuuichi Kokushou, Kazuma Kitamura, Shouta Yamada (Ritsumeikan Univ.), Masaya Yoshikawa (Meijyou Univ.), Takeshi Fujino (Ritsumeikan Univ.) VLD2008-139		 We have been studied the via-programmable-device VPEX (Via Programmable logic using EXclusive or array) whose logic elem... [more] VLD2008-139
pp.77-82
ICD 2008-12-12
13:45		 Tokyo Tokyo Inst. Tech., Ohokayama Campus, Kokusa-Kouryu-Kaikan Improvement of Logic Element used in Via programmable logic device VPEX
Tomohiro Nishimoto, Masahide Kawarasaki, Eiji Hasegawa, Tomohiro Terakawa, Takeshi Fujino (Ritsumei Univ) ICD2008-122		 We have been studied the via-programmable device (Via Programmable logic using EXclusive or array) whose logic element c... [more] ICD2008-122
pp.101-106
ICD 2008-12-12
14:10		 Tokyo Tokyo Inst. Tech., Ohokayama Campus, Kokusa-Kouryu-Kaikan The Development of CAD Design Tools for Via Programmable Logic Device VPEX
Yuuichi Kokushou, Masahide Kawarasaki, Kouta Ishibashi, Tomohiro Nishimoto, Kazuma Kitamura (Ritsumeikan Univ), Masaya Yoshikawa (Meijyou Univ), Takeshi Fujino (Ritsumeikan Univ) ICD2008-123		 We have been studied the user-programmable device called VPEX(Via Programmable logic using Exclusive or array) which can... [more] ICD2008-123
pp.107-112
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]		 2007-11-20
16:00		 Fukuoka Kitakyushu International Conference Center Proposal and Circuit Performance Evaluation of Mask-less Via Programmable Device VPEX for EB Direct Writing
Masahide Kawarasaki, Akihiro Nakamura, Tomoaki Nishimoto, Yoshiaki Shitabayashi, Takeshi Fujino (Ritsumeikan Univ.) VLD2007-80 DC2007-35		 We propose the user-programmable device called VPEX (Via Programmable logic device using EXclusive-or array) which can c... [more] VLD2007-80 DC2007-35
pp.61-66
 Results 1 - 14 of 14  /   
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