IEICE Technical Committee Submission System
Conference Schedule		 Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 5 of 5  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
ED 2014-08-01
14:20		 Tokyo Kikai-Shinko-Kaikan Bldg. B3-1 Analysis of Mechanisms of Delay Time Generation in III-V DG MOSFETs
Yuki Yajima, Ryoko Ohama, Sachie Fujikawa, Hiroki I. Fujishiro (TUS) ED2014-57		 III-V semiconductors have attracted much attention as promising n-type channel materials for the future logic device to ... [more] ED2014-57
pp.25-28
SDM 2009-10-29
16:45		 Miyagi Tohoku University Current Voltage Characteristics of Si-MESFET on SOI Substrate
Toshiyuki Abe, Yuichiro Tanushi, Shin-Ichiro Kuroki, Koji Kotani, Takashi Ito (Tohoku Univ.) SDM2009-122		 We simulate current-voltage characteristics of scaled Si metal semiconductor field effect transistors (MESFETs) and show... [more] SDM2009-122
pp.27-30
VLD, ICD 2008-03-07
16:10		 Okinawa TiRuRu New technology of independent-gate controlled Double-Gate transistor for system LSI
Yu Hiroshima, Keisuke Okamoto, Keisuke Koizumi, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2007-168 ICD2007-191		 New design technology of independent-gate controlled Double-Gate transistor realized high density design more than FinFE... [more] VLD2007-168 ICD2007-191
pp.69-74
VLD, ICD 2008-03-07
16:35		 Okinawa TiRuRu New design technology of independent-Gate controlled Stacked type 3D transistor for system LSI
Yu Hiroshima, Keisuke Okamoto, Keisuke Koizumi, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2007-169 ICD2007-192		 New design technology of Independent-Gate controlled Stacked type 3D transistor has feature of Independent-gate controll... [more] VLD2007-169 ICD2007-192
pp.75-80
ICD, VLD 2006-03-10
16:00		 Okinawa   Impact of Three-Dimensional Transistor on the pattern area reduction for ULSI
Shigeyoshi Watanabe (Shonan Inst. of Tech.) 		The impact of three-dimensional transistors, double-gate transistor, FinFET, and surrounding gate transistor (SGT) on th... [more] VLD2005-133 ICD2005-250
pp.67-72
 Results 1 - 5 of 5  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan