IEICE Technical Committee Submission System
Conference Schedule		 Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 4 of 4  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
HWS, VLD [detail] 2020-03-04
16:00		 Okinawa Okinawa Ken Seinen Kaikan
(Cancelled but technical report was issued)		 Pixel-based Mask Optimization with Lagrangian Relaxation and Boundary Flipping
Rina Azuma, Yukihide Kohira (Univ. of Aizu), Tomomi Matsui, Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama (KIOXIA) VLD2019-105 HWS2019-78		 Due to miniaturization of process technology, progressing manufacturing process by optical lithography is required. In r... [more] VLD2019-105 HWS2019-78
pp.65-70
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]		 2018-12-07
14:10		 Hiroshima Satellite Campus Hiroshima Process Variation-aware Model-based OPC using 0-1 Quadratic Programming
Rina Azuma, Yukihide Kohira (Univ. of Aizu), Tomomi Matsui, Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama, Shigeki Nojima (TMC) VLD2018-70 DC2018-56		 Due to continuous shrinking of Critical Dimensions (CD) of layout pattern in VLSI, advances of manufacturing process in ... [more] VLD2018-70 DC2018-56
pp.209-214
VLD, IPSJ-SLDM 2018-05-16
15:50		 Fukuoka Kitakyushu International Conference Center Pixel-based OPC using Quadratic Programming for Mask Optimization
Rina Azuma, Yukihide Kohira (Univ. of Aizu) VLD2018-3		 Due to continuous shrinking of Critical Dimensions (CD) in semiconductor manufacturing, advance of process technology in... [more] VLD2018-3
pp.31-36
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2015-12-02
14:55		 Nagasaki Nagasaki Kinro Fukushi Kaikan [Invited Talk] EDA Research Activities in The University of Texas at Austin
Tetsuaki Matsunawa (Toshiba) VLD2015-50 DC2015-46		 International competition in EDA research is getting more intense.
In major international conference, such as DAC or IC... [more]		 VLD2015-50 DC2015-46
p.73
 Results 1 - 4 of 4  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan