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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF | 2022-06-08 14:00 |
Ibaraki | CCS, Univ. of Tsukuba (Primary: On-site, Secondary: Online) |
 RECONF2022-19 |
Data has increased dramatically in recent years, and it is important to speed up parallel data processing using multiple... [more] | RECONF2022-19 p.86 |
| VLD, HWS [detail] | 2022-03-07 13:15 |
Online | Online | [Memorial Lecture]
An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers Lingxiao Hou, Yutaka Masuda, Tohru Ishihara (Nagoya Univ.) VLD2021-83 HWS2021-60 |
The logarithmic approximate multiplier proposed by Mitchell provides an efficient alternative to accurate multipliers in... [more] | VLD2021-83 HWS2021-60 p.43 |
| ICM, IPSJ-CSEC, IPSJ-IOT | 2021-05-13 10:05 |
Online | Online | Parallelism optimization method for analytical processing on hybrid cloud. Kaori Murase, Shinichi, Satoshi Kaneko, Kouichi Murayama (Hitachi, Ltd.) ICM2021-3 |
A hybrid data analytics platform that consists of data lake on on-premise and servers for analytical processing on publi... [more] | ICM2021-3 pp.13-18 |
| RECONF | 2020-05-29 10:25 |
Online | Online | FPGA-based human motion estimation based on amalgamated data from multiple sensors Xin Du, Yutaka Shinkai, Mizuki Itoh, Yoshiki Yamaguchi (Tsukuba Univ.) RECONF2020-12 |
This study proposes an FPGA-based system for identifying and estimating human motion by detecting data from sensors in d... [more] | RECONF2020-12 pp.65-70 |
| CPSY | 2012-10-12 15:10 |
Hiroshima | Shared Data Management Scheme for Java Layer-Unified Coarse Grain Task Parallel Processing Yuuki Ochi, Akimasa Yoshida (Toho Univ.) CPSY2012-39 |
In parallel processing on multicore processors, the layer-unified coarse grain task parallel processing scheme, which ex... [more] | CPSY2012-39 pp.49-54 |
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| RECONF | 2012-05-30 11:25 |
Okinawa | Tiruru (Naha Okinawa, Japan) | A Domain Specific Language and Toolchain for Runtime Binary Acceleration Takaaki Miyajima (Keio Univ.), David Thomas (Imperial), Hideharu Amano (Keio Univ.) RECONF2012-22 |
Computationally intensive applications can be off-loaded to FPGAs and GPUs to reduce execution time. However, choosing a... [more] | RECONF2012-22 pp.125-130 |
| VLD | 2012-03-06 15:30 |
Oita | B-con Plaza | CDFG Transformation Based on Speculation Exploiting Implicit Parallelism in Behavioral Synthesis Shinji Ohno (Nagoya Univ.), Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.) VLD2011-129 |
In recent years, circuit design in languages with higher abstraction level has been widely noticed to address the proble... [more] | VLD2011-129 pp.55-60 |
| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-25 15:55 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | Simultaneous Optimization of a CDFG Structure and a Schedule Based on Super-node Representation Akira Hirata, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) SIP2011-77 ICD2011-80 IE2011-76 |
In high-level synthesis, control-data flow graphs(CDFGs) are frequently used to describe the behavior of circuits since ... [more] | SIP2011-77 ICD2011-80 IE2011-76 pp.101-105 |
| RECONF | 2011-09-27 09:25 |
Aichi | Nagoya Univ. | A Design Framework for relieving a HW Bottleneck FPGAs Connected with a High-Speed Data Bus Koichi Araki, Yukinori Sato, Yasushi Inoguchi (JAIST) RECONF2011-33 |
As reconfigurable devices with a PCI-Express interface appear in the market, the data transfer speed between the reconfi... [more] | RECONF2011-33 pp.63-68 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] | 2011-03-19 14:45 |
Okinawa | Parallel C code generation from Simulink models Takahiro Kumura (NEC/Osaka Univ.), Masato Edahiro, Yuichi Nakamura (NEC), Nagisa Ishiura (Kwansei Gakuin Univ.), Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) CPSY2010-80 DC2010-79 |
This paper proposes a method to generate parallel C code from models developed on the Simulink which is a model-based ... [more] |
CPSY2010-80 DC2010-79 pp.303-308 |
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| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 15:30 |
Kanagawa | Keio Univ (Hiyoshi Campus) | A Consideration of Window Join Operator over Data Streams by using FPGA Yuta Terada, Takefumi Miyoshi (UEC), Hideyuki Kawashima (Univ. Tsukuba), Tsutomu Yoshinaga (UEC) VLD2010-111 CPSY2010-66 RECONF2010-80 |
An implementation technique of window join operator by using FPGA is studied in order to improve the performance. Window... [more] | VLD2010-111 CPSY2010-66 RECONF2010-80 pp.181-186 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-12-01 10:45 |
Fukuoka | Kyushu University | An Effective Processing Method for Parallel Loops on FPGA with PCI-Express Koichi Araki, Yukinori Sato, Yasushi Inoguchi (JAIST) RECONF2010-47 |
As FPGAs with a PCI-Express Interface appear in the market, the data transter speed between FPGA and other units, such a... [more] | RECONF2010-47 pp.49-54 |
| RECONF | 2009-05-14 16:10 |
Fukui | Performance evaluation of an auto-generation algorithm of hardware modules for an FPGA-based general-purpose biochemical simulator Tomonori Ooya, Hideki Yamada, Tomoya Ishimori, Yuichiro Shibata (Nagasaki Univ), Yasunori Osana (Seikei Univ), Masato Yoshimi (Doshisha Univ), Yuri Nishikawa, Hideharu Amano, Akira Funahashi, Noriko Hiroi (Keio Univ), Kiyoshi Oguri (Nagasaki Univ) RECONF2009-7 |
One of the obvious advantages of FPGA-based reconfigurable computing is customizability of a tradeoff point between perf... [more] | RECONF2009-7 pp.37-42 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 14:15 |
Fukuoka | Kitakyushu Science and Research Park | A Method of Processing Data-Parallel Tasks on Multi-Context Reconfigurable Processor Koichi Araki, Yukinori Sato, Yasushi Inoguchi (Japan Advanced Institute of Science and Technology) RECONF2008-41 |
A Multi-context Reconfigurable Processor (MRP) can treat various tasks with hardware. However, in the case of treating a... [more] | RECONF2008-41 pp.15-20 |
| DE | 2007-07-03 09:55 |
Miyagi | Akiu hot springs (Sendai) | A Scheme for Distributed and Parallel XML Query Processing using Remote Proxy Makoto Yui, Jun Miyazaki (NAIST), Shunsuke Uemura (Nara Sangyo Univ), Hirokazu Kato (NAIST) DE2007-58 |
In this paper, we focus on one aspect of distributed XQuery processing which is data exchange between processor elements... [more] | DE2007-58 pp.217-222 |
| ICD, IPSJ-ARC | 2007-05-31 13:15 |
Kanagawa | Effect of Data Prefetching on Chip MultiProcessor Naoto Fukumoto, Tomonobu Mihara, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) |
Chip MultiProcessors (or CMPs) can achieve higher performance by means of exploiting thread level parallelism. Increasin... [more] | ICD2007-20 pp.19-24 |
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| MSS | 2005-08-22 13:00 |
Aichi | Aichi Prefectural University | On Approximate Computation of MaxPARAdeg for Acyclic Well-Structured Data-Flow Program Nets Tomohiro Takai, Shingo Yamaguchi, Qi-Wei Ge, Minoru Tanaka (Yamaguchi Univ) |
This paper discusses approximate computation of the maximum degree of parallelism, denoted $MaxPARAdeg$, for a subclass ... [more] | CST2005-14 pp.1-6 |
| MSS | 2005-01-27 13:25 |
Tokyo | Univ. of Electro-Communications | A Parallel Computing System on Data Grid Environment using Process Migration Tsuguhiro Kondo, Hirotsugu Kakugawa (Hiroshima Univ.) |
In the data grid technology, technique of the parallel processing with many computing nodes is used to achieve efficient... [more] | CST2004-44 pp.31-36 |
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