Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
VLD |
2013-03-05 10:25 |
Okinawa |
Okinawa Seinen Kaikan |
An Acceleration method and its evaluation for Coarse Grained Reconfigurable Circuit Synthesis Nobuyuki Araki, Takashi Kambe (Kinki Univ.) VLD2012-144 |
High level synthesis for Coarse-grained architecture Reconfigurable Computing(CGA-RC) from high-level description is urg... [more] |
VLD2012-144 pp.49-54 |
RECONF |
2012-09-18 10:20 |
Shiga |
Epock Ritsumei 21, Ritsumeikan Univ. |
JPEG encoder design improvement and its evaluation for Dynamic Reconfigurable Circuit Hajime Sawano, Nobuyuki Araki, Takashi Kambe (Kinki Univ.) RECONF2012-26 |
Reconfigurable Computing (RC) has been proposed as a new paradigm to address the conflicting design requirements of high... [more] |
RECONF2012-26 pp.13-18 |
RECONF |
2012-09-19 13:40 |
Shiga |
Epock Ritsumei 21, Ritsumeikan Univ. |
A Circuit Synthesis Algorithm and Evaluation for Coarse Grained Dynamic Reconfigurable Circuits Nobuyuki Araki, Takashi Kambe (Kinki Univ.) RECONF2012-42 |
High level synthesis for Coarse-grained architecture Reconfigurable Computing(CGA-RC) from high-level description is urg... [more] |
RECONF2012-42 pp.107-112 |
VLD |
2011-03-03 14:10 |
Okinawa |
Okinawaken-Danjo-Kyodo-Sankaku Center |
A Circuit Synthesis for Dynamic Reconfigurable Processor Nobuyuki Araki, Takashi Kambe (Kinki Univ.) VLD2010-131 |
Dynamic reconfiguraible processors can implement large-scale and complicated circuits by changing its configurations dur... [more] |
VLD2010-131 pp.87-92 |
VLD, CPSY, RECONF, IPSJ-SLDM |
2009-01-30 17:00 |
Kanagawa |
|
Fast Solution of Link Disjoint Path Algorithm on Parallel Reconfigurable Processor DAPDNA-2 Taku Kihara, Sho Shimizu, Shan Gao, Yutaka Arakawa, Naoaki Yamanaka (Keio Univ.), Akifumi Watanabe (IPFlex) VLD2008-125 CPSY2008-87 RECONF2008-89 |
In next generation network, a high level reliabilty is strong required. In a protection, which is the one of network sur... [more] |
VLD2008-125 CPSY2008-87 RECONF2008-89 pp.201-206 |
PN |
2008-08-08 10:55 |
Hokkaido |
Asari Classe Hotel |
A Study on High Speed Method of Link-Disjoint Path Calculation
-- A Parallel Multi-layer Path Calculation on DAPDNA-2 -- Taku Kihara, Sho Shimizu, Shan Gao, Yutaka Arakawa, Naoaki Yamanaka (Keio Univ.) PN2008-17 |
K Disjoint-Paths Pairs (KDPPs) is widely used in the network to keep survivability. It is known that the KDPPs often fai... [more] |
PN2008-17 pp.19-24 |
VLD, ICD |
2008-03-07 15:45 |
Okinawa |
TiRuRu |
A Circuit Design of Reed-Solomon Decoder using Dynamically Reconfigurable Processor Atsurou Yoshida, Yuji Higashi, Wataru Miyazaki, Teruhito Tanaka, Takashi Kambe (Kinki University) VLD2007-167 ICD2007-190 |
Reed-Solomon Decoder can correct continues error and it has been a popular technology for various
devices such as commu... [more] |
VLD2007-167 ICD2007-190 pp.65-68 |
RECONF, CPSY, VLD, IPSJ-SLDM |
2008-01-16 17:25 |
Kanagawa |
Hiyoshi Campus, Keio University |
Fast solution method of Set Cover Problem on parallel reconfigurable processor DAPDNA-2 Hiroyuki Ishikawa, Sho Shimizu, Yutaka Arakawa, Naoaki Yamanaka (Keio Univ.), Kosuke Shiba (IPFlex) VLD2007-116 CPSY2007-59 RECONF2007-62 |
This paper proposes a fast calculation method of the set cover problem, which is implemented on reconfigurable processor... [more] |
VLD2007-116 CPSY2007-59 RECONF2007-62 pp.67-72 |
ICD, VLD |
2006-03-10 13:35 |
Okinawa |
|
A Circuit Design of Reed-Solomon Decoder using Dynamically Reconfigurable Technology Teruhito Tanaka, Kouji Hatada, Tetsuya Konishi, Yoshikazu Odajima, Takashi Kambe (Kinki Univ.) |
Reed-Solomon Decoder can correct continued errors and it has been a popular technology for various devices such as commu... [more] |
VLD2005-128 ICD2005-245 pp.37-42 |