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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC, CPSY, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2024-03-22 10:15 |
Nagasaki | Ikinoshima Hall (Primary: On-site, Secondary: Online) |
Context Cache Design for Multicore RISC-V Processors Akira Yamazawa (Keio Univ), Tsutomu Itou, Suito Kazutoshi (AXELL), Nobuyuki Yamasaki (Keio Univ)  CPSY2023-44 DC2023-110 |
Today, programs are executed using multiple threads. When multiple threads are used for execution, a context switch occu... [more] | CPSY2023-44 DC2023-110 pp.35-40 |
| IT, RCS, SIP | 2023-01-24 10:25 |
Gunma | Maebashi Terrsa (Primary: On-site, Secondary: Online) |
An improved context tree switching method by dynamic expansion and pruning of context tree Masaya Ootsu, Hideki Yagi (UEC) IT2022-36 SIP2022-87 RCS2022-215 |
The Context Tree Weighting (CTW) method is a sequential lossless universal coding algorithm for tree sources with good p... [more] | IT2022-36 SIP2022-87 RCS2022-215 pp.42-47 |
| HIP | 2022-10-18 10:25 |
Kyoto | Kyoto Terrsa (Primary: On-site, Secondary: Online) |
Comparison of memory results between handwritten input and keyboard input Reina Sato, Hiroshi Kadota (KUT) HIP2022-51 |
As the implementation of ICT advances, there are more opportunities to learn using a keyboard in education. Therefore, i... [more] | HIP2022-51 pp.22-25 |
| IT | 2016-07-28 14:55 |
Fukuoka | Seminar House, Fukuoka Univ. | Calculation of Asymptotic Code Rate of Balanced Code with ICI Constraint Hiroshi Kamabe (Gifu Univ) IT2016-26 |
The asymptotic code rate of a constraint satisfying the ICI free and the balance constraints can be drived from a con... [more] |
IT2016-26 pp.31-36 |
| MICT, ASN, MoNA (Joint) |
2016-01-29 14:45 |
Kanagawa | Hotel Okada | Human behavior prediction using network-graph based context model in mobile environment Naoto Kawai, Ryoichi Shinkuma (Kyoto Univ.), Kazuhiro Yamaguchi (KDL) MoNA2015-49 |
In general, human behaviors depend on contextual factors like location, time, day, and companions. Therefore, it has bee... [more] | MoNA2015-49 pp.51-54 |
| AI | 2014-11-27 13:00 |
Fukuoka | A context-dependent meaning-understanding model based on the neuroscientific facts
-- Development and application of a content-addressable memory system equipped with the analog-digital element as a processor(neuron) and with the memory element(synapse) in the communication path between processors -- Miyuki Seino (Seino Information System) AI2014-16 |
In order to model the memory system in neocortical association area, it will be clarified that the system learns and mem... [more] | AI2014-16 pp.1-6 |
|
| SS | 2012-05-10 14:40 |
Ehime | Ehime Univ. | On Multi-Task Scheduling for Reducing Heap Memory Consumption Using Live Variable Analysis Hiroki Funase, Akio Nakata (Hiroshima City Univ.) SS2012-2 |
Multitasking system often consume more memory than singletasking system, because when context switching occurs, the runn... [more] | SS2012-2 pp.7-12 |
| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-25 13:55 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | Data-Transfer-Aware Memory Allocation for Dynamically Reconfigurable Accelerators in Heterogeneous Multicore Processors Yosuke Ohbayashi, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) SIP2011-74 ICD2011-77 IE2011-73 |
Accelerator cores in low-power heterogeneous multicore processors have multiple memory modules to increase the data acce... [more] | SIP2011-74 ICD2011-77 IE2011-73 pp.77-82 |
| RECONF | 2010-09-17 11:00 |
Shizuoka | Shizuoka University (Faculty of Eng., Hall 2) | Removing context memory from Multi-context Dynamically Reconfigurable Processors Hideharu Amano, Masayuki Kimura, Nobuaki Ozaki (Keio Univ.) RECONF2010-34 |
Although context memory or configuration cache is a key mechanism for quick dyna mic reconfiguration of multi-context ... [more] |
RECONF2010-34 pp.97-102 |
| HIP | 2008-12-18 - 2008-12-19 |
Miyagi | RIEC | Influences of explicit learning for spatial layout on contextual cueing effect in visual search Takuro Mano, Satoshi Shioiri, Kazumichi Matsumiya, Ichiro Kuriki (Tohoku Univ.) HIP2008-123 |
When some of the particular set of layouts are repeatedly presented in a visual search task, participants learn the disp... [more] | HIP2008-123 pp.1-5 |
| ICD, IPSJ-ARC | 2008-05-14 11:15 |
Tokyo | Design of a Multi-Context Field-Programmable VLSI Using Ferroelectric-Based Functional Pass-Gates Noriaki Idobata, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) ICD2008-28 |
Multi-Context FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching betw... [more] | ICD2008-28 pp.57-62 |
|
| IT | 2005-07-22 15:20 |
Osaka | Osaka Prefecture Univ. | An Algorithm of Bayes Coding for FSMX Sources to Reduce Required Memory Size Akira Nakano, Naoto Kobayashi, Toshiyasu Matsushima (Waseda Univ.) |
Bayes code is one of universal source codings, such that a class of the probabilistic model of source is known but the p... [more] | IT2005-50 pp.47-52 |
| ISEC, IPSJ-CSEC | 2004-07-21 11:10 |
Tokushima | Tokushima Univ. | Protecting Memories in Multitask OSes
-- Tampering Detection -- Toru Egashira, Yu Inamura, Atsushi Takeshita (NTT DoCoMo) |
This paper provides the design of an integrity check function, which detects in-process data tampering done by the other... [more] | ISEC2004-45 pp.27-34 |
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