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Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-17
15:15
Kanagawa   Design and Implementation of High Performance Stencil Computer by using Mesh Connected FPGA Arrays
Ryohei Kobayashi, Shinya Takamaeda-Yamazaki, Kenji Kise (Tokyo Tech) VLD2012-134 CPSY2012-83 RECONF2012-88
We develop an effective stencil computation accelerator by using multiple FPGAs, which employs 2D-mesh architecture conn... [more] VLD2012-134 CPSY2012-83 RECONF2012-88
pp.159-164
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