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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, IPSJ-SLDM | 2018-05-16 15:00 |
Fukuoka | Kitakyushu International Conference Center | Non-volatile Power Gating for Data Cache with Dynamic Line-selection Sosuke Akiba, Kimiyoshi Usami (SIT)  VLD2018-2 |
In the whole of CPU, the proportion of energy consumption of the cache is increasing. Non-volatile Power Gating(NVPG) is... [more] | VLD2018-2 pp.19-24 |
| ICD, CPSY, CAS | 2017-12-14 15:10 |
Okinawa | Art Hotel Ishigakijima | Evaluation of Variations and Reliabilities of Drowsy Cache Type Adiabatic FinFET SRAM Tomotaka Tanaka, Yasuhiro Takahashi, Toshikazu Sekine (Gifu Univ.) CAS2017-77 ICD2017-65 CPSY2017-74 |
This paper inspects the differences of static noise margin of 4 types of SRAM circuits. These circuits are analyzed thre... [more] | CAS2017-77 ICD2017-65 CPSY2017-74 pp.71-74 |
| CPSY, DC, IPSJ-ARC (Joint) [detail] |
2016-08-10 11:15 |
Nagano | Kissei-Bunka-Hall (Matsumoto) | An Impact of In-Network Caching on Energy Saving for ISP Networks Kota Nojima, Takayuki Shiroma, Takuma Nakajima, Masato Yoshimi, Celimuge Wu, Tsutomu Yoshinaga (UEC) CPSY2016-33 |
Internet traffic is increasing year by year, and is expected to be double of that of 2016 in 2020. It is also estimated ... [more] | CPSY2016-33 pp.223-228 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 10:50 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Cache Energy Reduction by Switching between L1 High Power and Low Power Cache under DVFS Environment Kaoru Saito, Ryotaro Kobayashi (Toyohashi Univ of Tech), Hajime Shimada (Nagoya Univ.) CPSY2015-72 |
Current CPU utilizes cache memory for decreasing an access speed gap between CPU and main memory. But the cache occupie... [more] |
CPSY2015-72 pp.63-68 |
| CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] | 2015-03-07 09:45 |
Kagoshima | Energy Reduction of BTB by focusing on Number of Branches per Cache Line Hiroki Yamamoto, Ryotaro Kobayashi (TUT), Hajime Shimada (NU) CPSY2014-177 DC2014-103 |
Recent processors exploit Instruction Level Parallelism to improve performance, but it's limited by control dependency. ... [more] | CPSY2014-177 DC2014-103 pp.89-94 |
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| ICD, CPSY | 2014-12-01 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Poster Presentation]
A transparent on-chip instruction cache for reducing power and energy consumption of NV microcontrollers Dahoo Kim, Itaru Hida, Tetsuya Asai, Masato Motomura (Hokkaido Univ) ICD2014-82 CPSY2014-94 |
Demands for low energy microcontrollers which are used in sensor nodes have been increasing in recent years. Also most m... [more] | ICD2014-82 CPSY2014-94 p.43 |
| ICD | 2013-04-11 16:45 |
Ibaraki | Advanced Industrial Science and Technology (AIST) | Spin-Transfer Torque RAM Cache Energy Reduction Using Zero-Data Flags Yuta Kimi, Jinwook Jung, Yohei Nakata, Masahiko Yoshimoto, Hiroshi Kawaguchi (Kobe Univ.) ICD2013-10 |
In this paper, we propose an energy reduction scheme for Spin-Transfer Torque RAM (STT-RAM) Caches. Introducing STT-RAM ... [more] | ICD2013-10 pp.47-52 |
| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-25 15:05 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | Simultaneous Optimization of Cache Way Selection and Code Placement for Reducing the Memory Access Energy Consumption Junshi Takata (Kyushu Univ.), Tohru Ishihara (Kyoto Univ.), Koji Inoue (Kyushu Univ.) SIP2011-76 ICD2011-79 IE2011-75 |
The paper proposes a technique which simultaneously finds the optimal cache way allocation and code placement for given ... [more] | SIP2011-76 ICD2011-79 IE2011-75 pp.89-94 |
| ICD, IPSJ-ARC | 2007-05-31 11:30 |
Kanagawa | The Potential of Temperature-Aware Configurable Cache on Energy Reduction Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) |
Active power used to be the primary contributor to total power dissipation of CMOS designs, but with the technology sca... [more] |
ICD2007-19 pp.13-18 |
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| ICD | 2005-12-15 15:15 |
Kochi | Evaluation of energy consumption for High-Performance / Low-Leakage Caches based on Always Active line Reiko Komiya (Fukuoka Univ.), Koji Inoue, Kazuaki Murakami (Kyushu Univ.) |
So far we proposed a cache management technique to alleviate the negative effect of low-leakage caches. This technique m... [more] | ICD2005-189 pp.37-42 |
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