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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2023-12-08 13:50 |
Nagasaki | ARKAS SASEBO (Primary: On-site, Secondary: Online) |
A Multiple Target Seed Generation Method for Random Pattern Resistant Faults Using a Compatible Fault Set on Built-in Self Test Takanobu Sone, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.)  DC2023-88 |
In recent years, with high density of very large-scale integrated circuits, it has become impractical to store a large n... [more] | DC2023-88 pp.7-12 |
| DC | 2017-12-15 15:30 |
Akita | Akita Study Center, The Open University of Japan | A Test Clock Observation Method Using Time-to-Digital Converters for Built-In Self-Test in FPGAs Yousuke Miyake, Yasuo Sato, Seiji Kajihara (KIT) DC2017-75 |
A delay measurement method combining a logic BIST with a variable test clock has been proposed to improve field reliabil... [more] | DC2017-75 pp.37-42 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 14:45 |
Oita | B-ConPlaza | On-chip delay measurement for FPGAs Kentaro Abe, Yousuke Miyake, Seiji Kajihara, Yasuo Sato (KIT) VLD2014-109 DC2014-63 |
This paper describes an on-chip delay measurement method that targets a logic circuit on an FPGA. While advances in semi... [more] | VLD2014-109 DC2014-63 pp.245-250 |
| DC | 2013-12-13 13:25 |
Ishikawa | Variable Test-Timing Generation for Built-In Self-Test on FPGA Yasuo Sato, Munehiro Matsuura, Hitoshi Arakawa, Yousuke Miyake, Seiji Kajihara (Kyushu Inst. of Tech.) DC2013-69 |
This paper proposes a variable test-timing generation method that should be used for built-in self-test on FPGA. Applica... [more] | DC2013-69 pp.7-12 |
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| DC | 2012-06-22 13:50 |
Tokyo | Room B3-1 Kikai-Shinko-Kaikan Bldg | A Study on Fault Tolerant Test Pattern Generators for Reliable Built-in Self Test Yuki Fukazawa, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2012-11 |
In the BIST (built-in self-test) scheme, the occurrence of faults in BIST circuits, such as TPGs (test pattern generator... [more] | DC2012-11 pp.15-20 |
| DC | 2011-06-24 13:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Effective multi-cycle signatures in testable response analyzers Yuki Fukazawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2011-9 |
In the BIST (built-in self-test) scheme, we have proposed a concurrent testable response analyzer, called an encoding-ba... [more] | DC2011-9 pp.5-10 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-11-29 16:25 |
Fukuoka | Kyushu University | Experimental Evaluation of Built-in Test Pattern Generation with Image Decoders Yuka Iwamoto, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2010-63 DC2010-30 |
Built-in Self Test (BIST) is one of effective methods for testing today's very large-scale SoCs.In BIST scheme, a t... [more] | VLD2010-63 DC2010-30 pp.43-48 |
| DC, CPSY | 2009-04-21 15:45 |
Tokyo | Akihabara Satellite Campus, Tokyo Metropolitan Univ. | A design of testable response analyzers in built-in self-test Yuki Fukazawa, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) CPSY2009-7 DC2009-7 |
In the BIST(Built-in self-test) scheme, the occurrence of faults in BIST circuits, e.g., test generators and response co... [more] | CPSY2009-7 DC2009-7 pp.37-42 |
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