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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2020-11-17 09:30 |
Online | Online | Design of Nonvolatile SRAM Using SONOS Flash Cell and its Evaluation by Circuit Simulation Takaki Urabe, Koji Nii, Kazutoshi Kobayashi (KIT)  VLD2020-11 ICD2020-31 DC2020-31 RECONF2020-30 |
In this paper, we designed a layout of a nonvolatile SRAM memory using the SONOS Flash memory, and investigated its char... [more] | VLD2020-11 ICD2020-31 DC2020-31 RECONF2020-30 pp.1-5 |
| EMD | 2019-12-13 16:30 |
Tokyo | Arc energy calculation in re-striking phenomena in break operations of AgSnO2 contacts in inductive DC load conditions up to 20V-17A Makoto Hasegawa, Seika Tokumitsu (Chitose Inst. of Sci.&Tech.) EMD2019-47 |
AgSnO2 contacts were operated to break an inductive DC load circuit of 14V-7A, 14V-12A, 20V-7A, or 20V-17A with an appli... [more] | EMD2019-47 pp.25-30 |
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| VLD, CAS, MSS, SIP | 2016-06-17 09:50 |
Aomori | Hirosaki Shiritsu Kanko-kan | Design and Evaluation of MTJ-based Standard Cell Memory Junya Akaike, Masaru Kudo, Kimiyoshi Usami (SIT) CAS2016-19 VLD2016-25 SIP2016-53 MSS2016-19 |
With the spread of portable devices, products with high performance and long battery life are required. In this paper, w... [more] | CAS2016-19 VLD2016-25 SIP2016-53 MSS2016-19 pp.103-108 |
| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-16 16:00 |
Kanagawa | Break Even Time Evaluation of Run-Time Power Gating Control by On-chip Leakage Monitor Kensaku Matsunaga, Masaru Kudo (SIT), Yuya Ohta, Nao Konishi (SIT), Hideharu Amano (KU), Ryuichi Sakamoto, Mitaro Namiki (TUAT), Kimiyoshi Usami (SIT) VLD2012-118 CPSY2012-67 RECONF2012-72 |
Run-time Power Gating (RTPG) reduces leakage energy by turning off a power switch(PS) for idle periods of a circuit duri... [more] | VLD2012-118 CPSY2012-67 RECONF2012-72 pp.63-68 |
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| RECONF | 2008-05-23 09:00 |
Fukushima | The University of Aizu | Designing And Evaluating Dynamically Reconfigurable Processor with Power Gating Technique Yoshiki Saito (Keio Univ.), Toshiaki Shirai (Shibaura Inst.), Takuro Nakamura, Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi (Keio Univ.), Toshihiro Kashima, Mitsutaka Nakata, Seidai Takeda, Kimiyoshi Usami (Shibaura Inst.), Hideharu Amano (Keio Univ.) RECONF2008-10 |
A dynamically reconfigurable processor achieves high performance making the best use of high degree of parallelism with ... [more] | RECONF2008-10 pp.55-60 |
| PRMU | 2007-03-16 09:30 |
Okayama | Event detection from soccer video by using break term information Hiroki Atobe, Masao Izumi, Kunio Fukunaga (Osaka Prefecture Univ.) |
A soccer match is often interrupted when the event is occurred. The interrupted term is called 'break' term, which means... [more] | PRMU2006-259 pp.25-30 |
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