IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 5 of 5  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
ICM, NS, CQ, NV
(Joint)
2023-11-21
16:50
Ehime Ehime Prefecture Gender Equality Center
(Primary: On-site, Secondary: Online)
Proposal of a quality evaluation model for automatic design of information and communication systems based on Intent
Takayuki Kuroda, Toshiki Watanabe, Takuya Kuwahara, Ryosuke Hotchi (NEC) ICM2023-23
In recent years, research and development on automation of network operation has been actively pursued for the flexible ... [more] ICM2023-23
pp.2-7
VLD 2015-03-04
10:20
Okinawa Okinawa Seinen Kaikan Optimization of sequential circuit in gate-level pipelined self-synchronous circuit design
Atsushi Ito, Makoto Ikeda (The Univ. of Tokyo) VLD2014-177
With the down-scaling, circuit which has higher robustness is demanded. Dual-pipeline self synchronous circuit have inhe... [more] VLD2014-177
pp.135-140
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
09:15
Oita B-ConPlaza A study on automated arithmetic pipeline design on multi-FPGA systems
Yusuke Hirai, Katsuki Kyan, Makoto Arakaki (Univ. Ryukyus), Hideharu Amano (Keio Univ.), Naoyuki Fujita (JAXA), Yasunori Osana (Univ. Ryukyus) RECONF2014-34
Computational fluid dynamics (CFD), a powerful tool for aircraft
design and other mechanical designs is a major applica... [more]
RECONF2014-34
pp.1-6
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-28
10:05
Oita B-ConPlaza Optimization for gate-level pipelined self-synchrnous circuit
Atsushi Ito, Makoto Ikeda (Univ. of Tokyo) VLD2014-107 DC2014-61
With the down-scaling, circuit which has higher robustness is demanded. Dual-pipeline self synchronous circuit have inhe... [more] VLD2014-107 DC2014-61
pp.233-238
IE, ICD, VLD, IPSJ-SLDM [detail] 2013-10-07
11:20
Aomori   Construction of an Automatic Design Flow for Dual Pipelined Self-Synchronous Circuit
Atsushi Ito, Makoto Ikeda (Univ. of Tokyo) VLD2013-48 ICD2013-72 IE2013-48
With the down-scaling, circuit which has higher robustness is demanded. Dual-pipeline self synchronous circuit have inhe... [more] VLD2013-48 ICD2013-72 IE2013-48
pp.13-18
 Results 1 - 5 of 5  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan