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 Results 1 - 11 of 11  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2022-03-01
14:20
Tokyo Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online)
Evaluation of Efficiency for a Method to Locate High Power Consumption with Switching Provability
Ryu Hoshino, Taiki Utsunomiya, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2021-73
In recent years, as the high speed and miniaturization of LSIs have improved, it has become more difficult to test LSIs.... [more] DC2021-73
pp.51-56
VLD, DC, RECONF, ICD, IPSJ-SLDM
(Joint) [detail]
2020-11-17
10:30
Online Online Power Analysis Based on Probability Calculation of Small Regions in LSI
Ryo Oba, Ryu Hoshino, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech) VLD2020-13 ICD2020-33 DC2020-33 RECONF2020-32
Power consumption in LSI testing is higher than in functional mode since more switching activities occur. High power con... [more] VLD2020-13 ICD2020-33 DC2020-33 RECONF2020-32
pp.12-17
DC 2020-02-26
14:35
Tokyo   Power Analysis for Logic Area of LSI Including Memory Area
Yuya Kodama, Kohei Miyase, Daiki Takafuji, Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2019-93
Power consumption during LSI testing is higher than functional mode. Excessive IR-drop causes excessive delay, resulting... [more] DC2019-93
pp.43-48
DC 2020-02-26
15:00
Tokyo   Improving Controllability of Signal Transitions in the High Switching Area of LSI
Jie Shi, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2019-94
Power consumption in LSI testing is larger than in functional mode. High power consumption causes excessive IR-drop and ... [more] DC2019-94
pp.49-54
DC 2019-02-27
10:15
Tokyo Kikai-Shinko-Kaikan Bldg. Analysis of the hotspot distribution in the LSI
Yudai Kawano, Kohei Miyase (Kyutech), Shyue-Kung Lu (NTUST), Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2018-74
Performance degrading caused by high IR-drop in normal functional mode of LSI can be solved by improving power supply ne... [more] DC2018-74
pp.19-24
DC 2018-02-20
11:00
Tokyo Kikai-Shinko-Kaikan Bldg. Locating Hot Spots with Justification Techniques in a Layout Design
Yudai Kawano, Kohei Miyase, Seiji Kajihara, Xiaoqing Wen (Kyutech) DC2017-80
In general, power consumption during LSI testing is higher than functional operation. Excessive power consumption in at-... [more] DC2017-80
pp.19-24
DC 2015-06-16
15:00
Tokyo Kikai-Shinko-Kaikan Bldg. A Method to Identify High Test Power Areas in Layout Design
Kohei Miyase (Kyutech), Matthias Sauer, Bernd Becker (Univ. Freiburg), Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2015-18
The problems related to power consumption during at-speed testing is becoming more serious. Particularly, excessive peak... [more] DC2015-18
pp.13-18
DC 2011-06-24
16:20
Tokyo Kikai-Shinko-Kaikan Bldg. Low Power At-Speed Scan Testing for LOS Scheme by Test Vector Modification
Kohei Miyase, Yuta Uchinodan, Kazunari Enokimoto (KIT), Yuta Yamato (NAIST), Xiaoqing Wen, Seiji Kajihara (KIT), Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Verazel (Lirmm) DC2011-13
In this paper, we present a test vector modification method to reduce launch-to-capture power for LOS scheme. The propos... [more] DC2011-13
pp.29-34
DC 2011-02-14
10:25
Tokyo Kikai-Shinko-Kaikan Bldg. Capture-Safety Checking Based on Transition-Time-Relation for At-Speed Scan Test Vectors
Ryota Sakai, Kohei Miyase, Xiaoqing Wen (Kyushu Inst. of Tech.), Masao Aso, Hiroshi Furukawa (RMS), Yuta Yamato (Fukuoka Ind. Sci & Tech/Fundation FIST), Seiji Kajihara (Kyushu Inst. of Tech.) DC2010-60
Excessive capture power in at-speed scan testing may cause timing failures, resulting in test-induced yield loss. This h... [more] DC2010-60
pp.7-12
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2008-11-17
13:50
Fukuoka Kitakyushu Science and Research Park A Capture-Safe Test Generation Scheme for At-speed Scan Testing
Atsushi Takashima, Yuta Yamato, Hiroshi Furukawa, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyusyu Institute of Technology) VLD2008-62 DC2008-30
Capture-safety, defined as the avoidance of any timing error due to unduly high switching activity in capture mode durin... [more] VLD2008-62 DC2008-30
pp.13-18
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]
2007-11-20
10:30
Fukuoka Kitakyushu International Conference Center A Transition Delay Test Generation Method for Capture Power Reduction during At-Speed Scan Testing
Tomoaki Fukuzawa, Kohei Miyase, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara (KIT) VLD2007-71 DC2007-26
High power dissipation can occur when a response to the test vector is captured by flip-flops in at-speed scan testing, ... [more] VLD2007-71 DC2007-26
pp.7-12
 Results 1 - 11 of 11  /   
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