| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| HWS, VLD | 2023-03-03 09:55 |
Okinawa | (Primary: On-site, Secondary: Online) |
Track Assignment considering Routing Crossing Relations to Improve Feasibility in Bottleneck Channel Routing Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Molongo Mathieu, Makoto Minami, Katsuya Nishioka (Jedat)  VLD2022-101 HWS2022-72 |
Design automation that realizes analog integrated circuits to meet performance specifications in a small area is desired... [more] | VLD2022-101 HWS2022-72 pp.149-154 |
| NC, IBISML, IPSJ-BIO, IPSJ-MPS [detail] | 2022-06-29 14:20 |
Okinawa | (Primary: On-site, Secondary: Online) |
LSI implementation of analog CMOS majority circuit for neural network applications Satoshi Ono, Satoshi Moriya, Yuka Kanke, Hideaki Yamamoto (Tohoku Univ.), Yasushi Yuminaka (Gunma Univ.), Shigeo Sato (Tohoku Univ.) NC2022-27 IBISML2022-27 |
Majority logic circuit is a circuit whose output is the majority value of multiple binary inputs. It can be applied to b... [more] | NC2022-27 IBISML2022-27 pp.189-192 |
| VLD, HWS [detail] | 2022-03-07 09:35 |
Online | Online | Bottleneck Channel Routing to Reduce the Area of Analog VLSI Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Yukichi Todoroki, Makoto Minami (Jedat) VLD2021-77 HWS2021-54 |
Design automation that realizes analog integrated circuits to meet performance specifications in a small area is desired... [more] | VLD2021-77 HWS2021-54 pp.7-12 |
| NLP, MICT, MBE, NC (Joint) [detail] |
2022-01-23 09:50 |
Online | Online | Analog-circuit design of STDP learning rule with linear decay and its LSI implementation Satoshi Moriya, Tatsuki Kato (Tohoku Univ.), Yasushi Yuminaka (Gunma Univ.), Hideaki Yamamoto, Shigeo Sato, Yoshihiko Horio (Tohoku Univ.) NC2021-40 |
Spiking neural networks (SNNs) are expected to be the next generation of information processing technology to reduce the... [more] | NC2021-40 p.44 |
| SDM, ICD, ITE-IST [detail] | 2021-08-18 09:30 |
Online | Online | [Invited Talk]
Analog in-memory computing in FeFET based 1T1R array for low-power edge AI applications Daisuke Saito, Toshiyuki Kobayashi, Hiroki Koga (SONY), Yusuke Shuto, Jun Okuno, Kenta Konishi (SSS), Masanori Tsukamoto, Kazunobu Ohkuri (SONY), Taku Umebayashi (SSS), Takayuki Ezaki (SONY) SDM2021-36 ICD2021-7 |
Deep neural network (DNN) inference for edge AI requires low-power operation, which can be achieved by implementing mass... [more] | SDM2021-36 ICD2021-7 pp.33-37 |
| ICTSSL, CAS | 2020-01-30 13:10 |
Tokyo | [Invited Talk]
A Proposal of MOS LSI Analog Sign-Off Verification. Kimihiro Ogawa (Success Inc.) CAS2019-70 ICTSSL2019-39 |
In analog MOS circuit sign-off verification to guarantee design yield, it is well known that analog oriented methodology... [more] | CAS2019-70 ICTSSL2019-39 pp.35-41 |
|
| MBE, NC | 2019-10-12 11:45 |
Miyagi | LSI Implementation and Its Evaluation of an Izhikevich Model Neuron Analog MOS Circuit Yuki Tamura, Satoshi Moriya, Tatsuki Kato, Masao Sakuraba, Shigeo Sato, Yoshihiko Horio (Tohoku Univ.) MBE2019-44 NC2019-35 |
The Izhikevich neuron model, which can reproduce various spike activities with a small amount of calculation, is indispe... [more] | MBE2019-44 NC2019-35 pp.69-73 |
|
| NC, MBE (Joint) |
2018-10-19 14:00 |
Miyagi | Tohoku Univ. | A study on an Izhikevich Model Neuron MOS Circuit Yuki Tamura, Satoshi Moriya, Masao Sakuraba, Shigeo Sato (Tohoku Univ.) NC2018-13 |
The Izhikevich neuron, which can reproduce various spike activities with a small amount of calculation, is indispensable... [more] | NC2018-13 pp.1-5 |
| ICD | 2018-04-19 13:00 |
Tokyo | [Invited Talk]
VLSI implementation of chaotic Boltzmann machine for deep learning hardware Takashi Morie, Masatoshi Yamaguchi, Ichiro Kawashima, Hakaru Tamukoh (Kyushu Inst. of Tech.) ICD2018-4 |
The Boltzmann machine (BM) model has been proposed as an optimization-problem solver as well as a learning machine using... [more] | ICD2018-4 p.13 |
|
| DC | 2017-02-21 16:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Design for Evaluation of TSV based Interconnections in 3D-SIC
-- Interconnection Resistance Evaluation with Analog Boundary Scan -- Shuichi Kameyama (Ehime Univ./Fujitsu), Senling Wang, Hiroshi Takahashi (Ehime Univ.) DC2016-83 |
This paper introduces a concept of Design for Evaluation (DFE) that is a design method to embed circuits for quality eva... [more] | DC2016-83 pp.53-58 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 09:40 |
Kagoshima | The design of Via Programmable Analog(VPA) circuit and its performance evaluation compared to programmable analog circuit Keisuke Ueda, Ryohei Hori, Mitsuru Shiozaki, Toshio Kumamoto, Tomohiro Fujita, Takeshi Fujino (Ritsumeikan Univ.) CPM2013-110 ICD2013-87 |
Recently, programmable analog circuits are started to be used because initial development cost including mask cost is re... [more] | CPM2013-110 ICD2013-87 pp.13-18 |
|
| NC, NLP | 2013-01-25 14:10 |
Hokkaido | Hokkaido University Centennial Memory Hall | Development of a Spiking Neural Network System Consisting of a Dedicated Analog LSI Chip Controlled by an FPGA Michitaka Maeda, Frank Maldonado H., Takayuki Matsuo, Hideki Tanaka, Haichao Liang, Kenji Matsuzaka, Takashi Morie (Kyutech), Kazuyuki Aihara (Univ. of Tokyo) NLP2012-136 NC2012-126 |
Spiking neuron models, in which analog information is expressed by the timing of neuronal spike firing events, attract a... [more] | NLP2012-136 NC2012-126 pp.181-186 |
| EMCJ | 2013-01-11 14:45 |
Nagasaki | Nagasaki Univ. | Reduction technique for power supply noise of Analog-Digital Mixed Circuit Boards
-- Adjustment of Attached Resistor Method -- Shunsuke Baba, Shinichi Sasaki, Hitoshi Takakura, Hiroaki Matsumoto (Saga Univ) EMCJ2012-119 |
In analog-digital mixed circuit boards , noises from the digital side to the analog side through GND power supply layer ... [more] | EMCJ2012-119 pp.99-103 |
| ICD | 2012-12-18 13:30 |
Tokyo | Tokyo Tech Front | [Invited Talk]
CMOS analog mixed circuit and its applications Shouhei Kousai (Toshiba) ICD2012-118 |
Recent CMOS Analog VLSI has evolved with CMOS Digital circuits and has been enabled various and ubiquitous applications.... [more] | ICD2012-118 pp.115-120 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 11:20 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | Chip Design and Performance evaluation of Via Programmable Analog Circuit Keisuke Ueda, Ryo Nakazawa, Ryohei Hori, Mitsuru Shiozaki, Tomohiro Fujita, Takeshi Fujino (Ritsumeikan Univ.) CPM2012-121 ICD2012-85 |
Recently, programmable analog circuits are started to be used because initial development cost including mask cost is re... [more] | CPM2012-121 ICD2012-85 pp.49-54 |
| NLP | 2011-06-30 14:50 |
Hokkaido | Shari-cho Kohminkan: Yme-hall Shiretoko | Noise-Induced Phase Synchronization among Current-Noise-Sensitive Analog CMOS Oscillators Masakazu Matsuura, Akira Utagawa, Tetsuya Asai, Masato Motomura (Hokkaido Univ.) NLP2011-29 |
This report aims at the development of on-chip distributed clock sources on synchronous digital VLSIs. We focused attent... [more] | NLP2011-29 pp.23-28 |
| ICD, ITE-IST | 2010-07-23 09:15 |
Osaka | Josho Gakuen Osaka Center | Implementation and Evaluation of a CMOS Subthreshold Analog Amplifier using 0.5V Power Supply Tomochika Harada (Yamagata Univ.) ICD2010-30 |
[more] | ICD2010-30 pp.55-60 |
| EMCJ, ITE-BCT | 2010-03-12 15:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Design and Fabrication of On-chip Integrated Magnetic Field Probe using Low Noise Amplifier Shiori Namba, Wataru Kodate, Masahiro Yamaguchi (Tohoku Univ.), Shoji Kawahito (Shizuoka Univ.), Noboru Ishihara (Tokyo Inst. of Tech.) EMCJ2009-132 |
An on-chip integrated magnetic field probe has been designed and fabricated using CMOS technology. This probe will be us... [more] | EMCJ2009-132 pp.37-42 |
| CAS | 2010-01-28 16:35 |
Kyoto | Kyoudai-Kaikan Bldg. | [Fellow Memorial Lecture]
Study on video-frequency AD converter Masao Hotta (Tokyo City Univ.) CAS2009-71 |
Analog-to-Digital converters (ADCs) for video applications have made exciting progress in miniaturization and power redu... [more] | CAS2009-71 pp.43-48 |
| ICD | 2009-12-15 10:50 |
Shizuoka | Shizuoka University (Hamamatsu) | [Invited Talk]
History and Technology Trends of Si RF Analog LSI Developments
-- Emergence of New-Type Circuit Designers -- Tsuneo Tsukahara (Univ. of Aizu) ICD2009-96 |
The history of silicon RF analog circuits is described, focusing on the development of CMOS RF circuits. Moreover, the e... [more] | ICD2009-96 pp.111-116 |
[Return to Top Page]