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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2022-03-01 14:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. (Primary: On-site, Secondary: Online) |
SAT-based LFSR Seed Generation for Delay Fault BIST Kotaro Iwamoto, Satoshi Ohtake (Oita Univ.)  DC2021-74 |
So far, a one-pass LFSR seed generation method for delay fault BIST has been proposed. The method directly generates see... [more] | DC2021-74 pp.57-62 |
| IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] | 2019-01-30 11:20 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita (UTokyo) VLD2018-74 CPSY2018-84 RECONF2018-48 |
This paper proposes an incremental ATPG method to deal with multiple stuck-at faults. In order to generate the test set ... [more] | VLD2018-74 CPSY2018-84 RECONF2018-48 pp.13-18 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 13:50 |
Hiroshima | Satellite Campus Hiroshima | Study on the Applicability of ATPG Pattern for DFT Circuit Kohki Taniguchi, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2018-58 DC2018-44 |
With high integration of IC, small delay faults have occurred as the cause of a circuit failure. As a design-for-testabi... [more] | VLD2018-58 DC2018-44 pp.131-136 |
| VLD, CAS, MSS, SIP | 2016-06-16 10:10 |
Aomori | Hirosaki Shiritsu Kanko-kan | Automatic Test Pattern Generation for Multiple Stuck-At Faults: When Testing for Single Faults is Insufficient Conrad JinYong Moore, Amir Masoud Gharehbaghi, Masahiro Fujita (Univ. of Tokyo) CAS2016-3 VLD2016-9 SIP2016-37 MSS2016-3 |
As fabricated circuitry gets larger and denser, modern industrial ATPG techniques which focus on the detection of single... [more] | CAS2016-3 VLD2016-9 SIP2016-37 MSS2016-3 pp.13-18 |
| DC | 2016-02-17 10:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Reduction of open fault test pattern generation time by selection of adjacent lines for assigning logic value Kazui Fujitnai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) DC2015-88 |
As semiconductor technology is scaling down, open defects have often occurred at interconnect lines and vias. If logic v... [more] | DC2015-88 pp.13-18 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 13:00 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | Effective Orderings of Instances and Variable Assignments in SAT-based ATPG with Solution Reuse Kenji Ueda, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2012-83 DC2012-49 |
This report discusses the efficiency of iteratively solving various instances with solution reuse in test generation ba... [more] |
VLD2012-83 DC2012-49 pp.141-146 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 16:00 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A Method to Estimate the Number of Don't-Care Bits with Netlist Kohei Miyase, Seiji Kajihara, Xiaoqing Wen (KIT) VLD2012-104 DC2012-70 |
X-filling is often utilized so as to achieve test compression, test power reduction, or test quality improvement etc. i... [more] |
VLD2012-104 DC2012-70 pp.261-266 |
| DC | 2011-02-14 10:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Capture-Safety Checking Based on Transition-Time-Relation for At-Speed Scan Test Vectors Ryota Sakai, Kohei Miyase, Xiaoqing Wen (Kyushu Inst. of Tech.), Masao Aso, Hiroshi Furukawa (RMS), Yuta Yamato (Fukuoka Ind. Sci & Tech/Fundation FIST), Seiji Kajihara (Kyushu Inst. of Tech.) DC2010-60 |
Excessive capture power in at-speed scan testing may cause timing failures, resulting in test-induced yield loss. This h... [more] | DC2010-60 pp.7-12 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-03 14:05 |
Kochi | Kochi City Culture-Plaza | Optimizing Don't-Care Bit Rate Derived from X-Identification for Reduction of Switching Activity Isao Beppu (Kyushu Institute of Tech), Kohei Miyase (Kyushu Institute of Tech/JST), Yuta Yamato (Kyushu Institute of Tech), Xiaoqing Wen, Seiji Kajihara (Kyushu Institute of Tech/JST) VLD2009-55 DC2009-42 |
Increase of power dissipation and IR-drop during scan-shifting operation and/or capture operation is still challenging p... [more] | VLD2009-55 DC2009-42 pp.95-100 |
| DC | 2009-06-19 11:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Diagnositc Test Generation for Transition Faults Using a Stuck-at ATPG Tool Yoshinobu Higami, Yosuke Kurose, Satoshi Ohno, Hironori Yamaoka, Hiroshi Takahashi (Ehime Univ.), Yoshihiro Simizu, Takashi Aikyo (STARC), Yuzo Takamatsu (Ehime Univ.) DC2009-13 |
In modern high-speed LSIs, defects that cause timing failure occur often, and thus their detection and diagnosis are get... [more] | DC2009-13 pp.19-24 |
| DC | 2009-02-16 10:50 |
Tokyo | On the Acceleration of Redundancy Identification for Hard-to-ATPG faults Using SAT Yusuke Akiyama, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyusyu Univ.), Koji Yamazaki (Meiji Univ.) DC2008-70 |
Recently, 100% Fault coverage required in VLSI testing. However, ATPG algorithms can not classify all hard-to-test fault... [more] | DC2008-70 pp.13-18 |
|
| DC | 2008-02-08 16:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Current dissipation of Test pattern generators using ATPG vectors Hidekazu Tsuchiya, Takaya Abe, Takeshi Asakawa (Tokai univ.) DC2007-80 |
Recently, the operating speed of LSI is more fast and the scale of LSI is more larger. These induce increasing the dissi... [more] | DC2007-80 pp.83-88 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 10:30 |
Fukuoka | Kitakyushu International Conference Center | A Transition Delay Test Generation Method for Capture Power Reduction during At-Speed Scan Testing Tomoaki Fukuzawa, Kohei Miyase, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara (KIT) VLD2007-71 DC2007-26 |
High power dissipation can occur when a response to the test vector is captured by flip-flops in at-speed scan testing, ... [more] | VLD2007-71 DC2007-26 pp.7-12 |
| ICD, CPM | 2007-01-19 13:00 |
Tokyo | Kika-Shinko-Kaikan Bldg. | A Constrained Test Generation Method for Low Power Testing Yoshiaki Tounoue, Xiaoqing Wen, Seiji Kajihara (K I T), Kohei Miyase (JST), Tatsuya Suzuki, Yuta Yamato (K I T) |
High Power dissipation when the response to a test vector is captured by flip-flops in scan testing which may cause exce... [more] | CPM2006-148 ICD2006-190 pp.109-114 |
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