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Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF 2009-05-14
14:30		 Fukui   A Power of FPGA Reduction Using FPGA Routing Structure Based on the Small-World Network
Shoichi Nishida (Kumamoto Univ.), Yuzo Nishioka (Hitachi-Omron Terminal Solutions, Corp.), Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2009-4		 The performance of field-programmable gate arrays(FPGA) has improved dramatically owing to new process technology. But, ... [more] RECONF2009-4
pp.19-24
RECONF, CPSY, VLD, IPSJ-SLDM 2008-01-16
13:45		 Kanagawa Hiyoshi Campus, Keio University Evaluation of the Small-World Network Routing Structure for Cluster Based FPGAs
Yuzo Nishioka, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) VLD2007-108 CPSY2007-51 RECONF2007-54		 In deep sub-micron process, the wire delay exceeds the switching delay. The wire delay is dominant in the total delay. F... [more] VLD2007-108 CPSY2007-51 RECONF2007-54
pp.19-24
RECONF 2007-05-17
16:50		 Ishikawa Kanazawa Bunka Hall Detailed Evaluation of Delay for the Small-World Network Routing Structure
Yuzo Nishioka (Kumamoto Univ.), Hisashi Tsukiashi (Renesas Technology), Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2007-8		 The logic density of FPGA has improved rapidly. In deep sub-micron process, the wire delay increases because of the augm... [more] RECONF2007-8
pp.43-48
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