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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD 2010-09-27
15:30		 Kyoto Kyoto Institute of Technology [Invited Talk] Analog Circuit Optimization Using Pareto-Optimality
Yu Liu, Masato Yoshioka, Katsumi Homma, Yuzi Kanazawa (Fujitsu Labs), Toshiyuki Shibuya (Fujitsu Labs of America) VLD2010-45		 As the CMOS technology has benn continuously scaling down, the performances of analog/mixed-signal chips fluctuate remar... [more] VLD2010-45
pp.19-24
ICD, VLD 2007-03-08
14:10		 Okinawa Mielparque Okinawa Automatic routing methods which make modification after routing easy
Toshihiko Yokomaru, Takahide Yoshikawa, Yuzi Kanazawa (Fujitsu Labs.) 		In LSI designing with automatic routing tools, correcting logics or routing results after automatic routing is necessary... [more] VLD2006-132 ICD2006-223
pp.79-84
RECONF, CPSY, VLD, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]		 2006-11-29
15:30		 Fukuoka Kitakyushu International Conference Center Analysis of Maximum Switching Activities in Sequential Logic Circuits for Power Supply Integrity Validation
Hiroyuki Higuchi, Yuzi Kanazawa, Osamu Moriyama (Fujitsu Labs), Noriyuki Ito (Fujitsu) 		 [more] VLD2006-68 DC2006-55
pp.21-26
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