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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 16 of 16  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2016-12-16
13:00
Yamagata Sakata Sogo-Bunka Center(Sakata-City) High Reliable Memory Architecture with Adaptive Combination of Aging-Aware In-Field Self-Repair and ECC
Gian Mayuga, Yuta Yamato (NAIST), Yasuo Sato (KIT), Michiko Inoue (NAIST) DC2016-64
 [more] DC2016-64
pp.1-6
DC 2016-02-17
11:55
Tokyo Kikai-Shinko-Kaikan Bldg. Delay fault injection framework based on logic simulation with zero delay model
Shinji Kawasaki, Tomokazu Yoneda, Yuta Yamato, Michiko Inoue (NAIST) DC2015-90
Fault injection is a technique to re-create faulty behavior of circuits and widely accepted method to evaluate soft erro... [more] DC2015-90
pp.25-30
DC 2016-02-17
14:25
Tokyo Kikai-Shinko-Kaikan Bldg. Built-In Self-Test with Combination of Weighted Random Pattern and Reseeding
Sayaka Satonaka, Tomokazu Yoneda, Yuta Yamato, Michiko Inoue (NAIST) DC2015-92
Built-In Self-Test (BIST) is widely used to reduce test cost. However, it is difficult to achieve high fault coverage wi... [more] DC2015-92
pp.37-42
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-01
13:50
Nagasaki Nagasaki Kinro Fukushi Kaikan Background Sequence Generation for Neighborhood Pattern Sensitive Fault Testing in Random Access Memories
Shin'ya Ueoka, Tomokazu Yoneda, Yuta Yamato, Michiko Inoue (NAIST) VLD2015-40 DC2015-36
The Neighborhood Pattern Sensitive Fault (NPSF) is widely discussed fault model for memories, and it occurs when a memor... [more] VLD2015-40 DC2015-36
pp.19-24
DC 2014-12-19
14:15
Toyama   Reliability of ECC-based Memory Architectures with Online Self-repair Capabilities
Gian Mayuga, Yuta Yamato, Tomokazu Yoneda (NAIST), Yasuo Sato (Kyutech), Michiko Inoue (NAIST) DC2014-70
 [more] DC2014-70
pp.19-24
DC 2013-12-13
13:00
Ishikawa   Efficient Scan-Based BIST Architecture for Application-Dependent FPGA Test
Keita Ito, Tomokazu Yoneda, Yuta Yamato, Kazumi Hatayama, Michiko Inoue (NAIST) DC2013-68
This paper presents a scan-based BIST architecture for testing of application-dependent circuits configured on FPGA.
I... [more]
DC2013-68
pp.1-6
DC 2013-02-13
16:40
Tokyo Kikai-Shinko-Kaikan Bldg. Data volume reduction method for unknown value handling in built-in self test used in field
Yuta Yoshimi (NAIST), Kazumi Hatayama, Yuta Yamato, Tomokazu Yoneda, Michiko Inoue (NAIST/JST) DC2012-90
Many approaches on test pattern compression targeted unknown value handling. It is because unknown values have impacts o... [more] DC2012-90
pp.61-66
DC 2012-06-22
16:10
Tokyo Room B3-1 Kikai-Shinko-Kaikan Bldg On Per-Cell Dynamic IR-Drop Estimation in At-Speed Scan Testing
Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue (NAIST) DC2012-15
It is well known that dynamic IR-drop analysis consumes large amount of time even for a few clock cycles. This paper add... [more] DC2012-15
pp.39-44
DC 2011-06-24
16:20
Tokyo Kikai-Shinko-Kaikan Bldg. Low Power At-Speed Scan Testing for LOS Scheme by Test Vector Modification
Kohei Miyase, Yuta Uchinodan, Kazunari Enokimoto (KIT), Yuta Yamato (NAIST), Xiaoqing Wen, Seiji Kajihara (KIT), Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Verazel (Lirmm) DC2011-13
In this paper, we present a test vector modification method to reduce launch-to-capture power for LOS scheme. The propos... [more] DC2011-13
pp.29-34
DC 2011-02-14
10:25
Tokyo Kikai-Shinko-Kaikan Bldg. Capture-Safety Checking Based on Transition-Time-Relation for At-Speed Scan Test Vectors
Ryota Sakai, Kohei Miyase, Xiaoqing Wen (Kyushu Inst. of Tech.), Masao Aso, Hiroshi Furukawa (RMS), Yuta Yamato (Fukuoka Ind. Sci & Tech/Fundation FIST), Seiji Kajihara (Kyushu Inst. of Tech.) DC2010-60
Excessive capture power in at-speed scan testing may cause timing failures, resulting in test-induced yield loss. This h... [more] DC2010-60
pp.7-12
DC 2010-02-15
15:40
Tokyo Kikai-Shinko-Kaikan Bldg. High Speed X-Fault Diagnosis with Partial X-Resolution
Kohei Miyase (Kyushu Inst. of Tech.), Yusuke Nakamura (Panasonic Communications Software Co.,Ltd.), Yuta Yamato, Xiaoqing Wen, Seiji Kajihara (Kyushu Inst. of Tech.) DC2009-76
Defects behavior of ultra small size and high speed LSI is getting complicated. It makes localization of fault site and ... [more] DC2009-76
pp.69-74
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2009-12-03
14:05
Kochi Kochi City Culture-Plaza Optimizing Don't-Care Bit Rate Derived from X-Identification for Reduction of Switching Activity
Isao Beppu (Kyushu Institute of Tech), Kohei Miyase (Kyushu Institute of Tech/JST), Yuta Yamato (Kyushu Institute of Tech), Xiaoqing Wen, Seiji Kajihara (Kyushu Institute of Tech/JST) VLD2009-55 DC2009-42
Increase of power dissipation and IR-drop during scan-shifting operation and/or capture operation is still challenging p... [more] VLD2009-55 DC2009-42
pp.95-100
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2008-11-17
13:50
Fukuoka Kitakyushu Science and Research Park A Capture-Safe Test Generation Scheme for At-speed Scan Testing
Atsushi Takashima, Yuta Yamato, Hiroshi Furukawa, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyusyu Institute of Technology) VLD2008-62 DC2008-30
Capture-safety, defined as the avoidance of any timing error due to unduly high switching activity in capture mode durin... [more] VLD2008-62 DC2008-30
pp.13-18
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]
2007-11-20
10:30
Fukuoka Kitakyushu International Conference Center A Transition Delay Test Generation Method for Capture Power Reduction during At-Speed Scan Testing
Tomoaki Fukuzawa, Kohei Miyase, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara (KIT) VLD2007-71 DC2007-26
High power dissipation can occur when a response to the test vector is captured by flip-flops in at-speed scan testing, ... [more] VLD2007-71 DC2007-26
pp.7-12
R 2007-09-14
13:40
Kochi Kochi Univ. of Technology An expanded Per-Test X-Fault Diagnosis Method for LSI Circuits
Yusuke Nakamura, Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Seiji Kajihara (KIT), K. K. Saluja (Univ. of Wisconsin) R2007-33
The behavior of defects has become complex and more than one defects often occur in a single circuit due to shrinking fe... [more] R2007-33
pp.23-28
ICD, CPM 2007-01-19
13:00
Tokyo Kika-Shinko-Kaikan Bldg. A Constrained Test Generation Method for Low Power Testing
Yoshiaki Tounoue, Xiaoqing Wen, Seiji Kajihara (K I T), Kohei Miyase (JST), Tatsuya Suzuki, Yuta Yamato (K I T)
High Power dissipation when the response to a test vector is captured by flip-flops in scan testing which may cause exce... [more] CPM2006-148 ICD2006-190
pp.109-114
 Results 1 - 16 of 16  /   
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