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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 7 of 7  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2021-02-05
Online Online A Test Generation Method Using Information of Easily Testable Functional Time Expansion Model
Kenta Nakamura, Yuta Ishiyama, Toshinori Hosokawa (Nihon Univ.) DC2020-76
 [more] DC2020-76
DC 2021-02-05
Online Online A Don't Care Filling Method of Control Signals Based on Non-scan Field Testability at Register Transfer Level
Yuki Ikegaya, Yuta Ishiyama, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2020-77
A field testing that monitors the values of circuit outputs and internal signal lines during function mode is used as on... [more] DC2020-77
CPSY, DC, IPSJ-ARC [detail] 2020-07-31
Online Online A Generation Method of Easily Testable Functional Time Expansion Models Using Testability Measure Based on Data Amount
Kenta Nakamura, Toshinori Hosokawa, Yuta Ishiyama (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) CPSY2020-13 DC2020-13
 [more] CPSY2020-13 DC2020-13
HWS, VLD [detail] 2020-03-06
Okinawa Okinawa Ken Seinen Kaikan
(Cancelled but technical report was issued)
A Test Generation Method for Resistive Open Faults Using Partial MAX-SAT solver
Hiroshi Yamazaki, Yuta Ishiyama, Tatsuma Matsuta, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2019-131 HWS2019-104
In VLSI testing, stuck-at fault model and transition fault model have been widely used. However, with advance of semicon... [more] VLD2019-131 HWS2019-104
(Joint) [detail]
Ehime Ehime Prefecture Gender Equality Center A Generation Method of Easily Testable Functional k Time Expansion Model for a Transition Fault Model Using Controller Augmentation and Partial Scan Designs
Yuta Ishiyama, Toshinori Hosokawa, Yuki Ikegaya (Nihon Univ.) VLD2019-43 DC2019-67
One of the challenges on VLSI testing is to reduce the area overhead and test application time of design-for-testability... [more] VLD2019-43 DC2019-67
DC, SS 2019-10-24
Kumamoto Kumamoto Univ. A Non-scan Online Test Based on Covering n-Time State Transition
Yuki Ikegaya, Yuta Ishiyama, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) SS2019-19 DC2019-47
As one of the means to avoid the fault due to the deteriorate over time of VLSI, online test is used to monitor the outp... [more] SS2019-19 DC2019-47
DC 2019-02-27
Tokyo Kikai-Shinko-Kaikan Bldg. A Compaction Method for Test Sensitization State in Controllers
Yuki Ikegaya, Yuta Ishiyama, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.) DC2018-80
One of the challenges on VLSI testing is to reduce the area overhead of design-for-testability and to increase the fault... [more] DC2018-80
 Results 1 - 7 of 7  /   
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