IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
... (for ESS/CS/ES/ISS)
Tech. Rep. Archives
... (for ES/CS)
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 5件中 1~5件目  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, DC, IPSJ-ARC
(Joint) [detail]
2018-08-01
18:30
Kumamoto Kumamoto City International Center
Takeharu Ikezoe, Hideharu Amano (Keio Univ.), Junya Akaike, Kimiyoshi Usami, Masaru Kudo (SIT), Keizo Hiraga, Yusuke Shuto, Kojiro Yagami (Sony SS) CPSY2018-32
 [more] CPSY2018-32
pp.229-234
VLD, HWS
(Joint)
2018-03-02
10:30
Okinawa Okinawa Seinen Kaikan Implementation of Reconfigurable Accelerator Cool Mega-Array Using MTJ-based Nonvolatile Flip-Flop Enabling to Verify Stored Data
Junya Akaike, Kimiyoshi Usami, Masaru Kudo (SIT), Hideharu Amano, Takeharu Ikezoe (Keio Univ.), Keizo Hiraga, Yusuke Shuto, Kojiro Yagami (Sony SS) VLD2017-122
As a method of reducing the power consumption of the flip-flop circuit, there is a nonvolatile flip-flop (NVFF) that ena... [more] VLD2017-122
pp.199-204
ICD 2017-04-21
09:35
Tokyo   [Invited Lecture] Architectures and energy performance of nonvolatile SRAM for core-level nonvolatile power-gating
Daiki Kitagata, Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara (Tokyo Inst. of Tech.) ICD2017-10
Architectures and energy performance of nonvolatile SRAM (NV-SRAM) are demonstrated for nonvolatile power-gating (NVPG) ... [more] ICD2017-10
pp.51-56
ICD, SDM 2012-08-02
16:20
Hokkaido Sapporo Center for Gender Equality, Sapporo, Hokkaido Static noise margin and energy performance analyses of a nonvolatile SRAM cell using pseudo-spin-MOSFET
Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara (Tokyo Inst. Tech.) SDM2012-75 ICD2012-43
 [more] SDM2012-75 ICD2012-43
pp.65-70
MRIS, ITE-MMS 2011-10-14
11:15
Niigata Kashiwazaki energy hall, Niigata [Invited Talk] Nonvolatile Logic Systems Based on CMOS/Spintronics Hybrid Technology: An Overview
Satoshi Sugahara, Yusuke Shuto, Syuuichiro Yamamoto (Tokyo Insr. of Tech.) MR2011-18
 [more] MR2011-18
pp.63-70
 5件中 1~5件目  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan