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Committee Date Time Place Paper Title / Authors Abstract Paper #
HWS 2018-04-13
Fukuoka   Energy Evaluation of FPGA Pairing Implementation with Pipeline Modular Multiplier
Yusuke Nagahama, Daisuke Fujimoto, Junichi Sakamoto, Tsutomu Matsumoto (YNU) HWS2018-5
Energy consumption and latency are important features of dedicated hardware bilinear pairing calculators. However publi... [more] HWS2018-5
Tokyo   An FPGA Implementation of Optimal Ate Pairing Hardware using Pipeline Type Modular Multiplier for BN Curve over 254 bit Prime Field
Yusuke Nagahama (YNU), Daisuke Fujimoto (NAIST), Tsutomu Matsumoto (YNU)
(To be available after the conference date) [more]
EMM, ISEC, SITE, ICSS, IPSJ-CSEC, IPSJ-SPT [detail] 2016-07-15
Yamaguchi   A Faster Hardware for 254-bit Prime-Field Pairing with Dedicated Pipeline Modular Multipliers and Inverters
Daisuke Fujimoto, Yusuke Nagahama, Tsutomu Matsumoto (YNU) ISEC2016-36 SITE2016-30 ICSS2016-36 EMM2016-44
 [more] ISEC2016-36 SITE2016-30 ICSS2016-36 EMM2016-44
IT, ISEC, WBS 2016-03-10
Tokyo The University of Electro-Communications A Multiplier Architecture for Finite Field of 254bit-Prime Square Order Based on Pipelined 32bit Montgomery Multipliers
Yusuke Nagahama, Daisuke Fujimoto, Tsutomu Matsumoto (YNU) IT2015-116 ISEC2015-75 WBS2015-99
Bilinear Pairing is a major tool to realize advanced cryptographic functionality such as searchable encryption, aggregat... [more] IT2015-116 ISEC2015-75 WBS2015-99
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