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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
ICD |
2009-04-14 10:40 |
Miyagi |
Daikanso (Matsushima, Miyagi) |
A 0.56-V 128kb 10T SRAM Using Column Line Assist (CLA) Scheme Shusuke Yoshimoto, Yusuke Iguchi, Shunsuke Okumura, Hidehiro Fujiwara, Hiroki Noguchi (Kobe Univ.), Koji Nii (Renesas Technology Corp.), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2009-6 |
We present a small-area 10T SRAM cell without half selection problem. As well, the proposed 10T cell achieves a faster a... [more] |
ICD2009-6 pp.27-32 |
ICD |
2009-04-14 11:05 |
Miyagi |
Daikanso (Matsushima, Miyagi) |
A 7T/14T Dependable SRAM and Its Array Structure to Avoid Half Selection Shunsuke Okumura, Hidehiro Fujiwara, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST-CREST) ICD2009-7 |
We propose a novel dependable SRAM with 7T cells and their array structure that avoids a half-selection problem. The dep... [more] |
ICD2009-7 pp.33-38 |
VLD, IPSJ-SLDM |
2008-05-09 14:35 |
Hyogo |
Kobe Univ. |
A Dependable SRAM with high-reliability mode and high-speed mode. Shunsuke Okumura, Hidehiro Fujiwara, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) |
We propose a novel dependable SRAM with 7T memory cell pair, and introduce a new concept, “quality of a bit (QoB)” for i... [more] |
VLD2008-12 pp.31-36 |
ICD, SDM |
2007-08-24 15:40 |
Hokkaido |
Kitami Institute of Technology |
An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi (Kobe Univ.), Koji Nii (Kobe Univ./Renesas Technology), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) SDM2007-167 ICD2007-95 |
This paper demonstrates that an 8T memory cell can be alternative design to a 6T cell in a future highly-integrated SRAM... [more] |
SDM2007-167 ICD2007-95 pp.139-144 |
ICD, ITE-IST |
2007-07-26 17:30 |
Hyogo |
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A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing Shunsuke Okumura, Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita (Kobe Univ.), Koji Nii (Kobe Univ./Renesas Technology), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2007-53 |
We propose a low-power non-precharge-type two-port SRAM for video processing. The proposed memory cell (MC) has ten tran... [more] |
ICD2007-53 pp.95-100 |
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