| Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail] |
2019-11-15
16:35 |
Ehime |
Ehime Prefecture Gender Equality Center |
Mask Optimization Considering Process Variation by Subgradient Method
Yukihide Kohira, Rina Azuma (Univ. of Aizu), Tomomi Matsui, Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama (KIOXIA) |
(To be available after the conference date) [more] |
|
| HWS, VLD |
2019-02-27
15:20 |
Okinawa |
Okinawa Ken Seinen Kaikan |
Design Flow of Circuits with Multiple Supply Voltages for Power Reduction in General-Synchronous Framework
Masataka Aoki, Yukihide Kohira (Univ. of Aizu) |
In general-synchronous framework (g-frame), in which a clock is not assumed to be distributed to all registers simultane... [more] |
VLD2018-102 HWS2018-65
pp.55-60 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail] |
2018-12-07
14:10 |
Hiroshima |
Satellite Campus Hiroshima |
Process Variation-aware Model-based OPC using 0-1 Quadratic Programming
Rina Azuma, Yukihide Kohira (Univ. of Aizu), Tomomi Matsui, Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama, Shigeki Nojima (TMC) |
Due to continuous shrinking of Critical Dimensions (CD) of layout pattern in VLSI, advances of manufacturing process in ... [more] |
VLD2018-70 DC2018-56
pp.209-214 |
| CAS, SIP, MSS, VLD |
2018-06-14
16:15 |
Hokkaido |
Hokkaido Univ. (Frontier Research in Applied Sciences Build.) |
Acceleration of Analytical Placement by Wire Length Prediction using Machine Learning
Tatsuki Hoshiba, Yukihide Kohira (Univ. of Aizu) |
In recent LSI design, it is difficult to obtain a placement that satisfies both design constraints and specifications du... [more] |
CAS2018-14 VLD2018-17 SIP2018-34 MSS2018-14
pp.75-80 |
| VLD, IPSJ-SLDM |
2018-05-16
15:50 |
Fukuoka |
Kitakyushu International Conference Center |
Pixel-based OPC using Quadratic Programming for Mask Optimization
Rina Azuma, Yukihide Kohira (Univ. of Aizu) |
Due to continuous shrinking of Critical Dimensions (CD) in semiconductor manufacturing, advance of process technology in... [more] |
VLD2018-3
pp.31-36 |
VLD, HWS
(Joint) |
2018-03-01
09:50 |
Okinawa |
Okinawa Seinen Kaikan |
Clustering for Reduction of Power Consumption and Area on Post-Silicon Delay Tuning
Kota Muroi, Yukihide Kohira (Univ. of Aizu) |
Due to progressing process technology, yield of chips is reduced by timing violation caused by delay variation of gates ... [more] |
VLD2017-107
pp.109-114 |
| VLD |
2017-03-01
14:50 |
Okinawa |
Okinawa Seinen Kaikan |
Post-Silicon Delay Tuning Method for Power Reduction considering Yield Improvement
Hayato Mashiko, Yukihide Kohira (Univ. of Aizu) |
Due to the progress of the process technology in LSI, the yield of chips is reduced by the timing violation because of t... [more] |
VLD2016-104
pp.13-18 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail] |
2016-11-28
13:35 |
Osaka |
Ritsumeikan University, Osaka Ibaraki Campus |
Implementation Flow of General-Synchronous Circuits from RTL Representation for Xilinx FPGA
Manri Terada, Hayato Mashiko, Yukihide Kohira (Univ. of Aizu) |
Recently, the logic circuits are implemented to FPGA in many fields.
To achieve faster circuits, a design flow to imple... [more] |
VLD2016-48 DC2016-42
pp.25-30 |
| VLD |
2016-03-02
11:20 |
Okinawa |
Okinawa Seinen Kaikan |
Performance Improvement by Engineering Change Order in General-Synchronous Framework for Altera FPGA
Hayato Mashiko, Takuya Oba, Yukihide Kohira (Univ. of Aizu) |
Recently, the logic circuits are implemented to FPGA instead of ASIC in many fields. However, the circuit implemented to... [more] |
VLD2015-137
pp.149-154 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail] |
2015-12-02
16:20 |
Nagasaki |
Nagasaki Kinro Fukushi Kaikan |
Formulation to SAT for Acceleration in 1D Layout Area Minimization of CMOS circuits
Hayato Mashiko, Yukihide Kohira (Univ. of Aizu) |
In layout design for LSI circuits, the layout area is minimized to reduce the fabrication cost and to increase the yield... [more] |
VLD2015-51 DC2015-47
pp.81-86 |
| VLD |
2015-03-02
15:20 |
Okinawa |
Okinawa Seinen Kaikan |
Area Minimization of One-Dimensional Layout for MOS Circuits by SAT Solver and Simulated Annealing
Hayato Mashiko, Yukihide Kohira (Univ. of Aizu) |
[more] |
VLD2014-158
pp.31-36 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail] |
2014-11-26
11:10 |
Oita |
B-ConPlaza |
Technology Mapping Method for Low Power Consumption and High Performance in General-Synchronous Framework
Junki Kawaguchi, Yukihide Kohira (Univ. of Aizu) |
In general-synchronous framework, in which the clock is distributed periodically to each register but not necessarily si... [more] |
VLD2014-83 DC2014-37
pp.87-92 |
RCC, ASN, NS, RCS, SR
(Joint) |
2014-07-31
10:50 |
Kyoto |
Kyoto Terrsa |
[Poster Presentation]
Development of a Sensor Network to Measure Snow Depth using Arduino
Shunya Hosaka, Yosuke Moriai, Masamitsu Nakajima, Yukihide Kohira, Hiroshi Saito (Univ. Aizu) |
To reduce accident, traffic and economic paralysis, and effect for personal life caused by snow, we develop a sensor net... [more] |
RCC2014-26 NS2014-46 RCS2014-98 SR2014-27 ASN2014-45
pp.23-28(RCC), pp.1-6(NS), pp.55-60(RCS), pp.43-48(SR), pp.31-36(ASN) |
| VLD, IPSJ-SLDM |
2014-05-29
11:30 |
Fukuoka |
Kitakyushu International Conference Center |
LELECUT Triple Patterning Lithography Layout Decomposition using Positive Semidefinite Relaxation
Yukihide Kohira (Univ. of Aizu), Tomomi Matsui (Tokyo Tech), Yoko Yokoyama, Chikaaki Kodama (Toshiba), Atsushi Takahashi (Tokyo Tech), Shigeki Nojima, Satoshi Tanaka (Toshiba) |
One of the most promising techniques in the 14 nm logic node and beyond is triple patterning lithography (TPL). Recently... [more] |
VLD2014-6
pp.27-32 |
| VLD |
2014-03-04
13:50 |
Okinawa |
Okinawa Seinen Kaikan |
Local Pattern Modification Method for Lithographical ECO in Double Patterning
Yutaro Miyabe, Atsushi Takahashi, Tomomi Matsui (Tokyo Inst. of Tech.), Yukihide Kohira (Univ. of Aizu), Yoko Yokoyama (Toshiba) |
In advanced semiconductor manufacturing processes, even though a pattern is generated according to
a design rule, hot s... [more] |
VLD2013-149
pp.87-92 |
| VLD |
2014-03-05
16:10 |
Okinawa |
Okinawa Seinen Kaikan |
Implementation of General-Synchronous Circuits into FPGA using Multi-Domain Clock Skew Scheduling
Tatsuya Masui, Yukihide Kohira (Univ. of Aizu) |
Recently, instead of implementation into ASIC, implementation into FPGA is used in many fields. However, in general, cir... [more] |
VLD2013-167
pp.183-188 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail] |
2013-11-29
13:45 |
Kagoshima |
|
A Tuning Method of Programmable Delay Element with an Ordered Finite Set of Delay Values for Yield Improvement
Hayato Mashiko, Yukihide Kohira (Univ. of Aizu) |
Due to progressing the process technology in LSI, the yield of LSI chips is reduced by timing violations caused by delay... [more] |
VLD2013-99 DC2013-65
pp.275-280 |
| VLD, IPSJ-SLDM |
2013-05-16
09:50 |
Fukuoka |
Kitakyushu International Conference Center |
A Longest Path Algorithm for Differential Pair Net Considering Connectivity
Koji Yamazaki, Yukihide Kohira (Univ. of Aizu) |
In recent years, due to the speedup and miniaturization in LSI systems, PCB routing design uses many differential pair n... [more] |
VLD2013-3
pp.13-18 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail] |
2012-11-26
16:50 |
Fukuoka |
Centennial Hall Kyushu University School of Medicine |
A Delay Tuning Method of Programmable Delay Element with Two Delay Values for Yield Improvement
Hayato Mashiko, Yukihide Kohira (UoA) |
Due to progressing the process technology in LSI and increasing delay variations of interconnection and gate delays afte... [more] |
VLD2012-69 DC2012-35
pp.57-62 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail] |
2012-11-27
09:25 |
Fukuoka |
Centennial Hall Kyushu University School of Medicine |
An Acceleration Method by GPGPU for Analytical Placement using Quasi-Newton Method
Yukihide Kohira (UoA), Yasuhiro Takashima (Univ. of Kitakyushu) |
In this paper, we propose an acceleration method by GPGPU for an analytical placement method using a quasi-Newton method... [more] |
VLD2012-74 DC2012-40
pp.87-92 |