| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 14:55 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | An Approach to Selection of Classifiers and their Thresholds for Machine Learning Based Fail Chip Prediction Daichi Yuruki, Satoshi Ohtake (Oita Univ), Yoshiyuki Nakamura (Renesas Electronics)  VLD2017-36 DC2017-42 |
Today, semiconductor technologies have developed and advance the integration density of LSI circuits. A technique which... [more] |
VLD2017-36 DC2017-42 pp.55-60 |
| DC | 2017-02-21 12:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An Approach to Performance Improvement of Machine Learning Based Fail Chip Discrimination Daichi Yuruki, Satoshi Ohtake (Oita Univ), Yoshiyuki Nakamura (Renesas System Design) DC2016-77 |
Today, advancements of semiconductor technology have progress to high integration of LSI circuits. A technique which ke... [more] |
DC2016-77 pp.17-22 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2016-03-25 15:45 |
Nagasaki | Fukue Bunka Hall/Rodou Fukushi Center | A consideration on variation correction for fail prediction in LSI test Ryo Ogawa (NAIST), Yoshiyuki Nakamura (Renesas Semiconductor Package & Test Solutions), Michiko Inoue (NAIST) CPSY2015-158 DC2015-112 |
Recently, a test cost reduction using data mining has been attracted. It is expected to reduce the cost by predicting fa... [more] | CPSY2015-158 DC2015-112 pp.271-276 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 15:10 |
Oita | B-ConPlaza | A Method of Burn-in Fail Prediction of LSIs Based on Supervised Learning Using Cluster Analysis Shogo Tetsukawa, Seiya Miyamoto, Satoshi Ohtake (Oita Univ.), Yoshiyuki Nakamura (Renesas) VLD2014-110 DC2014-64 |
Production test of LSIs consists of several test phases such as wafer test phase, package test phase, burn-in test phase... [more] | VLD2014-110 DC2014-64 pp.251-256 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-29 08:30 |
Kagoshima | A Study of Burn-In Test Prediction by Data Mining Satoshi Nonoyama, Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.), Yoshiyuki Nakamura (Renesas Electronics) VLD2013-91 DC2013-57 |
[more] | VLD2013-91 DC2013-57 pp.221-226 |
|
| DC | 2010-02-15 09:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Statistical Method of Small Iddq Variance Outlier Detection Yoshiyuki Nakamura, Masashi Tanaka (NEC Electronics) DC2009-65 |
With manufacturing process advances, Iddq test becomes difficult due to its variance. Though ?Iddq or various methods we... [more] | DC2009-65 pp.1-5 |
| USN | 2008-05-22 15:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. (Tokyo) | [Invited Talk]
Ubiquitous Sensor Network for People's Media Takuichi Nishimura, Yoshiyuki Nakamura (AIST) USN2008-9 |
This paper shows an activity capture method of attendees and facilitators for indoor interactive workshops, which are ev... [more] | USN2008-9 pp.49-54 |
| OPE | 2004-12-14 13:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Wavelength division multiplexing optical filters for a multi-language serving spatial optical communicating terminal Hideo Itoh, Yoshiyuki Nakamura, Xin Lin, Takuichi Nishimura (AIST) |
[more] | OPE2004-176 pp.13-16 |
| OPE | 2004-12-14 16:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | PAL-SLM based CGH beam steering system for the location based information services Shunichi Osawa (Musashi Inst. Tech.), Hideo Itoh, Yoshiyuki Nakamura, Takuichi Nishimura, Xin Lin (AIST), Masamitsu Tokuda (Musashi Inst. Tech.) |
Multiple and simultaneous information providing technique using the spatial optical communication based on the computer-... [more] | OPE2004-181 pp.39-43 |
[Return to Top Page]