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Conference Papers (Available on Advance Programs) (Sort by: Date Descending)

Committee	Date Time	Place		Paper Title / Authors	Abstract	Paper #
ISEC	2010-09-10 10:45	Tokyo	Kikai-Shinko-Kaikan Bldg.	Electro Magnetic Analysis and Local Information of Cryptographic Hardware - part 2 - Hidekazu Morita, Tsutomu Matsumoto, Yoshio Takahashi, Junji Shikata (Yokohama National Univ.) ISEC2010-38	[more]	ISEC2010-38 pp.1-8
ISEC	2009-12-16 14:55	Tokyo	Kikai-Shinko-Kaikan Bldg.	Electro Magnetic Analysis and Local Information of Cryptographic Hardware Hidekazu Morita, Yoshio Takahashi, Tsutomu Matsumoto, Junji Shikata (Yokohama National Univ.)) ISEC2009-75	We have analyzed local information obtained by measuring electromagnetic waves radiated from multiple places on a FPGA i... [more]	ISEC2009-75 pp.29-35
ISEC	2008-09-12 16:35	Tokyo	Kikai-Shinko-Kaikan Bldg.	Estimating RSA Private-Keys Generated in Security Chips Tsutomu Matsumoto, Yoshio Takahashi (YNU) ISEC2008-71	For a particular instance of TPM - Trusted Platform Module, we have shown that the RSA private keys generated inside the... [more]	ISEC2008-71 pp.55-62
ISEC, IT, WBS	2008-02-29 09:20	Tokyo		Side Channel Attacks from Signal Lines of Cryptographic Modules -- Experiments for FPGA-Implemented AES -- Ryota Watanabe, Makoto Torikoshi, Yoshio Takahashi, Tsutomu Matsumoto (Yokohama National Univ.) IT2007-51 ISEC2007-148 WBS2007-82	[more]	IT2007-51 ISEC2007-148 WBS2007-82 pp.15-22
ISEC	2007-12-19 10:20	Tokyo	Kikai-Shinko-Kaikan Bldg.	How to design tables for power-analyses resistance of Table-network-based FPGA implementations of AES Makoto Torikoshi, Yoshio Takahashi, Tsutomu Matsumoto (Yokohama National Univ.) ISEC2007-114	Differential power analyses are statistical cryptanalytic methods to estimate the value of hidden cryptographic keys ins... [more]	ISEC2007-114 pp.11-18
ISEC, LOIS	2006-11-17 12:05	Chiba	Univ. of Tokyo(Kashiwa Campus)	Table-Network-Based FPGA Implementations of AES and Their Resistance Against Differential Power Analyses Tatsunori Tsujimura (Yokohama Nat'l Univ.), Yoshio Takahashi (Yokohama Nat'l Univ./NTT Data), Tsutomu Matsumoto (Yokohama Nat'l Univ.)	[more]	ISEC2006-100 OIS2006-58 pp.33-40
ISEC	2006-05-19 13:25	Tokyo	Kikai-Shinko-Kaikan Bldg.	Bit-Transition Differential Power Analysis on FPGA Implementaion of Block Cipher with Masking Countermeasure Yoshio Takahashi (NTT Data/Yokohama Nat'l Univ.), Tsutomu Matsumoto (Yokohama Nat'l Univ.), Akashi Satoh (IBM Japan)	[more]	ISEC2006-1 pp.1-6
ISEC	2005-12-16 11:05	Tokyo	Kikai-Shinko-Kaikan Bldg.	Side channel attacks against block cipher implementation on FPGA Yoshio Takahashi (NTT Data), Akashi Satoh (IBM Research), Nobuaki Umeda (NTT Data)	[more]	ISEC2005-111 pp.5-10
IT, WBS, ISEC	2005-03-17 16:35	Kyoto	Kyoto Univ.	Side channel attacks against block cipher implementaion on CPU Yoshio Takahashi (NTT Data), Toshinori Fukunaga, Hiroaki Ohtsuka, Masayuki Kanda (NTT)	[more]	IT2004-58 ISEC2004-114 WBS2004-173 pp.49-54

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