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Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD, SDM 2008-07-17
Tokyo Kikai-Shinko-Kaikan Bldg. A 45 nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations
Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka (Renesas Tech.), Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Katsuji Satomi, Hironori Akamatsu (Matsushita Elec.), Hirofumi Shinohara (Renesas Tech.) SDM2008-131 ICD2008-41
We develop 512 Kb SRAM module in 45 nm LSTP CMOS technology with the variation tolerant assist circuits against process ... [more] SDM2008-131 ICD2008-41
ICD, SDM 2007-08-24
Hokkaido Kitami Institute of Technology A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues
Satoshi Ishikura, M. Kurumada, Toshio Terano, Yoshinobu Yamagami, Naoki Kotani, Katsuji Satomi (Matushita Electric Industrial), Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara (Renesas Technology), Hironori Akamatsu (Matushita Electric Industrial) SDM2007-168 ICD2007-96
We propose a new 2port SRAM with a 8T single-read-bitline (SRBL) memory cell for 45nm SOCs. Access time tends to be slow... [more] SDM2007-168 ICD2007-96
ICD, SDM 2006-08-18
Hokkaido Hokkaido University A Stable SRAM Cell Design Against Simultaneously R/W Disturbed Accesses
Toshikazu Suzuki (Matsushita), Hiroyuki Yamauchi (Fukuoka Institute of Technology Univ.), Yoshinobu Yamagami, Katsuji Satomi, Hironori Akamatsu (Matsushita)
A guarantee obligation of keeping the cell-margin against a simultaneously read and write (R/W) disturbed accesses in th... [more] SDM2006-149 ICD2006-103
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