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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, IPSJ-SLDM 2010-05-20
13:05
Fukuoka Kitakyushu International Conference Center A Wide-Range Clock Synchronizer with Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS Control
Masafumi Onouchi, Yusuke Kanno, Makoto Saen, Shigenobu Komatsu (Hitachi), Yoshihiko Yasu, Koichiro Ishibashi (Renesas) VLD2010-7
A ``wide-range voltage-and-frequency clock synchronizer'' for maintaining synchronization during voltage-scaling transit... [more] VLD2010-7
pp.67-72
CPM, ICD 2008-01-17
14:30
Tokyo Kikai-Shinko-Kaikan Bldg [Special Invited Talk] In-situ measurement of supply-noise maps with millivolt accuracy and nanosecond-order time resolution
Yusuke Kanno, Yuki Kondoh (HCRL), Takahiro Irita, Kenji Hirose, Ryo Mori, Yoshihiko Yasu (Renesas Technology, Corp.), Shigenobu Komatsu, Hiroyuki Mizuno (HCRL) CPM2007-136 ICD2007-147
An in-situ measurement scheme for generating supply-noise maps, which can be conducted while running applications in pro... [more] CPM2007-136 ICD2007-147
pp.47-52
ICD, SDM 2007-08-23
15:25
Hokkaido Kitami Institute of Technology A 1.92us-wake-up time thick-gate-oxide power switch technique for ultra low-power single-chip mobile processors
Kazuki Fukuoka, Osamu Ozawa, Ryo Mori, Yasuto Igarashi, Toshio Sasaki, Takashi Kuraishi, Yoshihiko Yasu, Koichiro Ishibashi (Renesas Technology) SDM2007-153 ICD2007-81
A technique for controlling rush current and wake-up time of thick-gate-oxide power switches is described. Suppressing t... [more] SDM2007-153 ICD2007-81
pp.69-73
ICD, ITE-CE 2006-12-15
11:15
Hiroshima   Low Power SOC Design using Partial-Trench-Isolation ABC SOI for sub-100-nm LSTP technology
Osamu Ozawa, Kazuki Fukuoka, Yasuto Igarashi, Takashi Kuraishi, Yoshihiko Yasu, Yukio Maki, Takashi Ipposhi, Toshihiko Ochiai, Masayoshi Shirahata, Koichiro Ishibashi (Renesas)
 [more] ICD2006-163
pp.115-119
ICD 2006-05-25
13:30
Hyogo Kobe University Hierarchical Power Distribution with dozens of power domain in 90-nm Low-power SoCs
Yusuke Kanno (HCRL), Hiroyuki Mizuno (Hitachi), Yoshihiko Yasu, Kenji Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi (Renesas), Toshifumi Ishii (Hitachi ULSI), Tetsuya Yamada (HCRL), Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa (Renesas), Naohiko Irie (HCRL)
 [more] ICD2006-26
pp.25-30
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