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Committee Date Time Place Paper Title / Authors Abstract Paper #
IE, SIP, ICD, VLD, IPSJ-SLDM [detail] 2012-10-19
09:25		 Iwate Hotel Ruiz Design of a Packet-Transfer-Based Dynamic Reconfigurable VLSI Processor for Reduction of a Configuration Memory Size
Yoshichika Fujioka (Hachinohe Inst. of Tech.), Michitaka Kameyama (Tohoku Univ.) VLD2012-47 SIP2012-69 ICD2012-64 IE2012-71		 Register-transfer-level packet routing scheme is proposed for intra-chip data transfer to make the size of configuration... [more] VLD2012-47 SIP2012-69 ICD2012-64 IE2012-71
pp.39-44
ICD, IE, SIP, IPSJ-SLDM [detail] 2011-10-24
14:45		 Miyagi Ｉｃｈｉｎｏｂｏ(Sendai) Architecture of a Dynamically Reconfigurable VLSI Processor Based on Register-Transfer-Level Packet Transfer
Yoshichika Fujioka (Hachinohe Inst. of Tech.), Sho Takizawa, Michitaka Kameyama (Tohoku Univ.) SIP2011-64 ICD2011-67 IE2011-63		 Register-transfer-level packet routing scheme is proposed for intra-chip data transfer to make the size of configuration... [more] SIP2011-64 ICD2011-67 IE2011-63
pp.13-18
ICD, IPSJ-ARC 2007-06-01
16:15		 Kanagawa   Design of a highly parallel VLSI processor based on functional-unit-level packet data transfer scheme
Yoshichika Fujioka, Nobuhiro Tomabechi (Hachinohe Inst. Tech.), Michitaka Kameyama (Tohoku Univ.) ICD2007-34		 Until now, network on chip technology based on course grain packet data transfer was proposed. In this paper, fine grain... [more] ICD2007-34
pp.103-108
ICD 2005-12-15
11:45		 Kochi   VLSI Processor Architecture Based on Intra-Chip Packet Data Transfer Scheme
Yoshichika Fujioka, Nobuhiro Tomabechi (Hachinohe Inst. of Tech.), Michitaka Kameyama (Tohoku Univ.) 		 [more]
 Results 1 - 4 of 4  /   
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