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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM 2014-02-28
11:00
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Impact of Back Grind Damage on Si Wafer Thinning for 3D Integration
Yoriko Mizushima (Fujitsu Lab./Tokyo Inst. of Tech.), Youngsuk Kim (Tokyo Inst. of Tech./Disco), Tomoji Nakamura (Fujitsu Lab.), Ryuichi Sugie, Hideki Hashimoto (Toray Research Center), Akira Uedono (Univ. of Tsukuba), Takayuki Ohba (Tokyo Inst. of Tech.) SDM2013-167
Ultra-thin wafer is indispensable for bumpless 3D stacking. To know the thinning damage in detail, an atomic level defec... [more] SDM2013-167
pp.13-18
SDM 2012-03-05
15:25
Tokyo Kikai-Shinko-Kaikan Bldg. Influence of Via Stress on Surface Micro-roughness-induced Leakage Current in Through-Silicon Via Interconnects
Hideki Kitada (Univ. of Tokyo/Fujitsu Lab.), Nobuhide Maeda, Koji Fujimoto, Shoichi Kodama, Young Suk Kim (Univ. of Tokyo), Yoriko Mizushima (Univ. of Tokyo/Fujitsu Lab.), Tomoji Nakamura (Fujitsu Lab.), Takayuki Ohba (Univ. of Tokyo) SDM2011-183
 [more] SDM2011-183
pp.41-46
SDM 2012-03-05
15:55
Tokyo Kikai-Shinko-Kaikan Bldg. Characterization of Local Strain around Through Silicon Via Interconnect in Wafer-on-wafer Structures
Osamu Nakatsuka (Nagoya Univ.), Hideki Kitada, Young Suk Kim (Univ. of Tokyo), Yoriko Mizushima, Tomoji Nakamura (Fujitsu Lab.), Takayuki Ohba (Univ. of Tokyo), Shigeaki Zaima (Nagoya Univ.) SDM2011-184
We have investigated the local strain structure in a thinned Si layer stacked on Si substrate for wafer-on-a-wafer appli... [more] SDM2011-184
pp.47-52
SDM 2011-02-07
15:25
Tokyo Kikai-Shinko-Kaikan Bldg. Development of Low Temperature Bump-less TSV Process in 3D Stacking Technology
Hideki Kitada, Nobuhide Maeda (The Univ. of Tokyo), Koji Fujimoto (Dai Nippon Printing), Yoriko Mizushima, Yoshihiro Nakata, Tomoji Nakamura (Fujitsu Laboratories Ltd.), Takayuki Ohba (The Univ. of Tokyo) SDM2010-224
Diffusion behavior of Cu in Cu through-silicon-vias (TSVs) fabricated using low-temperature plasma enhanced chemical vap... [more] SDM2010-224
pp.49-53
ICD, SDM 2010-08-27
10:15
Hokkaido Sapporo Center for Gender Equality [Invited Talk] Development of sub-10um Thinning Technology using Actual Device Wafers
Nobuhide Maeda, Kim Youngsuk (Univ. of Tokyo), Yukinobu Hikosaka, Takashi Eshita (FSL), Hideki Kitada, Koji Fujimoto (Univ. of Tokyo), Yoriko Mizushima (Fujitsu Labs.), Kousuke Suzuki (DNP), Tomoji Nakamura (Fujitsu Labs.), Akihito Kawai, Kazuhisa Arai (DISCO), Takayuki Ohba (Univ. of Tokyo) SDM2010-141 ICD2010-56
200-mm and 300-mm device wafers were successfully thinned down to less than 10-μm. A 200-nm non-crystalline layer remain... [more] SDM2010-141 ICD2010-56
pp.95-97
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