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Committee Date Time Place Paper Title / Authors Abstract Paper #
MSS, CAS, SIP, VLD 2019-07-31
14:55		 Iwate Iwate Univ. Structurally Liveness and Boundedness Analysis of Petri Nets Using Circuit Flow Calculating for Structures Covered by Marked Graph
Yojiro Harie, Katsumi Wasaki (Shinshu Univ.) CAS2019-18 VLD2019-24 SIP2019-34 MSS2019-18		  [more] CAS2019-18 VLD2019-24 SIP2019-34 MSS2019-18
pp.77-82
MSS, CAS, IPSJ-AL [detail] 2018-11-12
15:50		 Shizuoka   Stability Subnet Detection of Petri Net by Circuit Flow-Matrix Transformation
Yojiro Harie, Katsumi Wasaki (Shinshu Univ.) CAS2018-64 MSS2018-40		 Petri net is a graphical and mathematical modeling tool describes distributed systems.
For dynamic analysis of Petri ne... [more]		 CAS2018-64 MSS2018-40
pp.37-42
MSS, CAS, IPSJ-AL [detail] 2018-11-12
16:15		 Shizuoka   A Method for Improving Memory Efficiency of the Reachability Graph Generation Process in General Petri Nets
Kohei Fujimori, Yojiro Harie, Katsumi Wasaki (Shinshu Univ.) CAS2018-65 MSS2018-41		 State space generator is one of the analysis functions of Petri net
design tool HiPS (Hierarchical Petri net Simulator)... [more]		 CAS2018-65 MSS2018-41
pp.43-47
MSS, CAS, IPSJ-AL [detail] 2016-11-24
13:25		 Hyogo Kobe Institute of Computing Development and evaluation of on-the-fly model checking for a Petri net verification tool (HiPS)
Yojiro Harie, Katsumi Wasaki (Shinshu Univ.) CAS2016-63 MSS2016-43		 This paper proposes an On-the-fly Fluent Linear Temporal Logic (FLTL) model checker using state space generation based o... [more] CAS2016-63 MSS2016-43
pp.31-35
SS, MSS 2016-01-25
15:45		 Ishikawa Shiinoki-Geihin-Kan On-the-fly Model Checker for a Petri Net Verification Tool(HiPS) by using Replacement LTL Formula to Event-Based Automaton
Yojiro Harie, Katsumi Wasaki (Shinshu Univ.) MSS2015-46 SS2015-55		 This paper proposes an On-the-fly Linear Temporal Logic (LTL) model checker using state space generation based on the Pe... [more] MSS2015-46 SS2015-55
pp.63-68
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