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Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD, ITE-IST 2011-07-22
10:25
Hiroshima Hiroshima Institute of Technology Analysis Methods of Substrate Sensitivity in an Analog Circiut
Satoshi Takaya, Yoji Bando (Kobe Univ.), Toru Ohkawa, Masaaki Souda, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami (MIRAI-Selete), Makoto Nagata (Kobe Univ.) ICD2011-28
Substrate noise sensitivity of an analog circuit consists of the sensitivity of a device and noise propagation from the ... [more] ICD2011-28
pp.73-78
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2010-11-29
11:20
Fukuoka Kyushu University A Consideration of Substrate Noise Sensitivity of Analog Elements
Satoshi Takaya, Yoji Bando, Takashi Hasegawa (Kobe Univ.), Toru Ohkawa, Masaaki Souda, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami (MIRAI-Selete), Makoto Nagata (Kobe Univ.) CPM2010-126 ICD2010-85
Measure substrate sensitivity of differential amplifiers in a 90 nm CMOS technology with more than 32 different geometor... [more] CPM2010-126 ICD2010-85
pp.13-17
ICD, ITE-IST 2010-07-22
10:20
Osaka Josho Gakuen Osaka Center In-situ Evaluation of Vth and AC Gain of 90 nm CMOS Differential Pair Transistors
Yoji Bando, Satoshi Takaya, Takashi Hasegawa (Kobe Univ.), Toru Ohkawa, Masaaki Souda, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami (MIRAI-Selete), Makoto Nagata (Kobe Univ.) ICD2010-23
 [more] ICD2010-23
pp.11-14
ICD 2009-12-14
13:30
Shizuoka Shizuoka University (Hamamatsu) [Poster Presentation] Simulation of Substrate Noise Impact on CMOS Analog Circuit
Satoshi Takaya, Yoji Bando, Makoto Nagata (Kobe Univ.) ICD2009-81
We have measured and simulated substrate noise impact on basic analog amplifier using 90-nm CMOS test chip. To measure s... [more] ICD2009-81
pp.31-34
ICD, ITE-IST 2009-10-01
10:00
Tokyo CIC Tokyo (Tamachi) Evaluation and Analysis of Substrate Noise in Microprocessor
Yoji Bando (Kobe Univ.), Daisuke Kosaka (A-R-Tec), Goichi Yokomizo, Kunihiko Tsuboi (STARC), Ying Shiun Li, Shen Lin (Apache), Makoto Nagata (Kobe Univ./A-R-Tec) ICD2009-35
An integrated power and substrate noise analysis environment targeting systems-on-chip (SoC) design was verified through... [more] ICD2009-35
pp.11-14
ICD, VLD 2007-03-07
17:00
Okinawa Mielparque Okinawa On-chip monitoring for sub-100-nm digital signal integrity
Yoji Bando, Koichiro Noguchi, Makoto Nagata (Kobe Univ.)
A compact on-chip signal monitor circuit uses voltage mode sensing by a source follower circuit with small input device ... [more] VLD2006-116 ICD2006-207
pp.61-66
 Results 1 - 6 of 6  /   
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