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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 8件中 1~8件目  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2020-01-24
10:20
Kanagawa Raiosha, Hiyoshi Campus, Keio University Virtual-Channel Implementation on Communication Circuit of FPGA Cluster by Qsys Interconnect
Naohisa Fukase, Akihisa Furuiti, Yasuyuki Miura, Tsukasa-Pierre Nakao (SIT) VLD2019-82 CPSY2019-80 RECONF2019-72
In recent days, in order to improve the performance of computer, methods using FPGA have been attracting attention. FPGA... [more] VLD2019-82 CPSY2019-80 RECONF2019-72
pp.169-174
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] 2016-01-19
10:40
Kanagawa Hiyoshi Campus, Keio University Circuit Design of Reconfigurable Logic and Comparison of the Methods
Junki Kato, Shigeyoshi Watanabe, Hiroshi Ninomiya, Manabu Kobayashi, Yasuyuki Miura (SIT) VLD2015-77 CPSY2015-109 RECONF2015-59
 [more] VLD2015-77 CPSY2015-109 RECONF2015-59
pp.1-6
SDM, ICD 2015-08-25
10:20
Kumamoto Kumamoto City Circuit Design of Reconfigurable Dynamic Logic and Estimation of Number of Elements
Junki Kato, Shigeyoshi Watanabe, Hiroshi Ninomiya, Manabu Kobayashi, Yasuyuki Miura (SIT) SDM2015-66 ICD2015-35
 [more] SDM2015-66 ICD2015-35
pp.47-52
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-29
10:45
Kanagawa Hiyoshi Campus, Keio University Circuit Design and Valuation of Reconfigurable Logic Circuit.
Junki Kato, Shigeyoshi Watanabe, Hiroshi Ninomiya, Manabu Kobayashi, Yasuyuki Miura (SIT) VLD2014-119 CPSY2014-128 RECONF2014-52
 [more] VLD2014-119 CPSY2014-128 RECONF2014-52
pp.35-40
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-27
16:50
Oita B-ConPlaza Circuit Design of Reconfigurable Dynamic Logic
Junki Kato, Shigeyoshi Watanabe, Hiroshi Ninomiya, Manabu Kobayashi, Yasuyuki Miura (Shonan Inst. of Tech.) CPM2014-126 ICD2014-69
 [more] CPM2014-126 ICD2014-69
pp.21-26
ICD, SDM 2014-08-05
14:20
Hokkaido Hokkaido Univ., Multimedia Education Bldg. Circuit Design of Reconfigurable Dynamic Logic Based on Double Gate MOSFETs
Junki Kato, Shigeyoshi Watanabe, Hiroshi Ninomiya, Manabu Kobayashi, Yasuyuki Miura (SIT) SDM2014-78 ICD2014-47
 [more] SDM2014-78 ICD2014-47
pp.87-92
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2008-11-17
15:25
Fukuoka Kitakyushu Science and Research Park Adaptive routing of the 2-D torus network based on a Turn model
Kazuya Matoyama, Yasuyuki Miura, Shigeyoshi Watanabe (Shonan Institute of Technology) RECONF2008-43
 [more] RECONF2008-43
pp.27-32
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2008-11-17
15:50
Fukuoka Kitakyushu Science and Research Park Hardware Implementation Costs of Adaptive Routing in the Hierarchical Interconnection Network
Masahiro Kaneko, Yasuyuki Miura, Shigeyoshi Watanabe (Shonan Institute of Technology) RECONF2008-44
By progress of VLSI technology, "On-Chip-Multiprocessor" which processes in parallel on a wafer has been realized, and a... [more] RECONF2008-44
pp.33-38
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