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Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2010-02-15
16:05
Tokyo Kikai-Shinko-Kaikan Bldg. Consideration of Open Faults Model Based on Digital Measurement of TEG Chip
Toshiyuki Tsutsumi (Meiji Univ.), Yasuyuki Kariya, Koji Yamazaki (Meiji Univ), Masaki Hashizume, Hiroyuki Yotsuyanagi (Tokushima Univ), Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu (Ehime Univ) DC2009-77
Countermeasures against an open fault in LSI testing become more important with advancement of LSI process technology. ... [more] DC2009-77
pp.75-80
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2008-11-17
14:15
Fukuoka Kitakyushu Science and Research Park Analysis of Open Fault using TEG Chip
Toshiyuki Tsutsumi, Yasuyuki Kariya, Koji Yamazaki (Meiji Univ), Masaki Hashizume, Hiroyuki Yotsuyanagi (Tokushima Univ), Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu (Ehime Univ) VLD2008-63 DC2008-31
The high integration of the semiconductor technology advances, and the fault detection and the failure diagnosis of LSI ... [more] VLD2008-63 DC2008-31
pp.19-24
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