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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD 2012-12-18
10:20		 Tokyo Tokyo Tech Front 28-nm HKMG GHz Digital Sensor for Detecting Dynamic Voltage Drops in Testing for Peak Power Optimization
Mitsuhiko Igarashi, Yoshio Takazawa, Yasuto Igarashi, Hiroaki Matsushita, Kan Takeuchi (Renesas Electronics) ICD2012-115		 We propose a dynamic voltage-drop sensor, which is fully digital so that it is easy to design into products and use for ... [more] ICD2012-115
pp.97-102
ICD, SDM 2012-08-03
13:10		 Hokkaido Sapporo Center for Gender Equality, Sapporo, Hokkaido A Fast-Transient-Response Digital Low-Dropout Regulator Comprising Thin-Oxide MOS Transistors in 40-nm CMOS process
Masafumi Onouchi, Kazuo Otsuga, Yasuto Igarashi, Toyohito Ikeya, Sadayuki Morita (Renesas Electronics), Koichiro Ishibashi (Univ. of Electro-Comm.), Kazumasa Yanagisawa (Renesas Electronics) SDM2012-82 ICD2012-50		 A digital low-dropout (LDO) regulator comprising only thin-oxide MOS transistors was developed. The input voltage to the... [more] SDM2012-82 ICD2012-50
pp.105-110
ICD, SDM 2007-08-23
15:25		 Hokkaido Kitami Institute of Technology A 1.92us-wake-up time thick-gate-oxide power switch technique for ultra low-power single-chip mobile processors
Kazuki Fukuoka, Osamu Ozawa, Ryo Mori, Yasuto Igarashi, Toshio Sasaki, Takashi Kuraishi, Yoshihiko Yasu, Koichiro Ishibashi (Renesas Technology) SDM2007-153 ICD2007-81		 A technique for controlling rush current and wake-up time of thick-gate-oxide power switches is described. Suppressing t... [more] SDM2007-153 ICD2007-81
pp.69-73
ICD, ITE-CE 2006-12-15
11:15		 Hiroshima   Low Power SOC Design using Partial-Trench-Isolation ABC SOI for sub-100-nm LSTP technology
Osamu Ozawa, Kazuki Fukuoka, Yasuto Igarashi, Takashi Kuraishi, Yoshihiko Yasu, Yukio Maki, Takashi Ipposhi, Toshihiko Ochiai, Masayoshi Shirahata, Koichiro Ishibashi (Renesas) 		 [more] ICD2006-163
pp.115-119
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