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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 8 of 8  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2020-02-27
17:20
Kagoshima Yoron-cho Chuou-Kouminkan Toward acceleration of matrix multiplication on homomorphic encryption library
Tetsuya Makita, Teppei Shishido (Waseda Univ.), Yasutaka Wada (Meisei Univ.), Keiji Kimura (Waseda Univ.) CPSY2019-96 DC2019-102
(To be available after the conference date) [more] CPSY2019-96 DC2019-102
pp.51-56
RECONF 2019-09-20
11:20
Fukuoka KITAKYUSHU Convention Center FPGA Implementation of Image Recognition with Multiple Simple Neural Networks for Higher Performance and Accuracy
Musashi Aoto, Shoya Hirukawa, Yasutaka Wada, Kazutaka Maruyama (Meisei Univ) RECONF2019-31
Object recognition on camera images is one of the most important technologies required to realize automatic driving syst... [more] RECONF2019-31
pp.57-62
EMM 2016-03-03
09:45
Kagoshima Yakushima Environ. and Cultural Vill. Center Stress-care Test and the Visualization for Health-care
Yasutami Chigusa, Yasutaka Wada, Mikoto Kurimoto, Yoshiyuki Yamazaki (TUT), Taizoh Hattori (TIU) EMM2015-90
 [more] EMM2015-90
pp.81-85
WIT 2015-10-26
11:15
Yamaguchi Kawatana Grand Hotel Pleasant sleeping method for media and helthcare
Yasutami Chigusa, Kyohei Ohtsu, Yasutaka Wada, Yoshiyuki Yamazaki (TUT), Taizoh Hattori (TIU)
 [more]
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
17:30
Kanagawa Hiyoshi Campus, Keio University A Cache to Cache Communication Strategy for Wireless 3D Multi-Core Processors
Masataka Matsumura (UEC), Masaaki Kondo (Univ. Tokyo), Hiroki Matsutani (Keio Univ.), Yasutaka Wada (Waseda Univ.), Hiroki Honda (UEC) VLD2014-152 CPSY2014-161 RECONF2014-85
The inductive-coupling 3D chip stacking technique has several advantages over TSV-based 3D stacking. For example, its ma... [more] VLD2014-152 CPSY2014-161 RECONF2014-85
pp.245-250
ITS, WBS
(Joint)
2009-12-09
15:25
Kumamoto Kumamoto University Interference Mitigation Performance of Wavelet Packet-based DS-UWB
Yasutaka Wada, Shigenobu Sasaki (Niigata Univ.) WBS2009-48
This paper investigates an interference mitigation scheme for direct sequence ultra-wideband (DS-UWB) wireless communica... [more] WBS2009-48
pp.67-72
ICD, IPSJ-ARC, IPSJ-EMB 2009-01-14
11:15
Osaka Shoushin Kaikan Performance Evaluation of Parallelizing Compiler Cooperated Heterogeneous Multicore Architecture Using Media Applications
Teruo Kamiyama, Yasutaka Wada, Akihiro Hayashi, Masayoshi Mase, Hirofumi Nakano, Takeshi Watanabe, Keiji Kimura, Hironori Kasahara (Waseda Univ.)
This paper describes a heterogeneous multicore architecture having accelerator cores in addition to general purpose core... [more] ICD2008-140
pp.63-68
ICD, SDM 2007-08-23
09:20
Hokkaido Kitami Institute of Technology Evaluation of Heterogeneous Multicore Architecture with AAC-LC Stereo Encoding
Hiroaki Shikano (Hitachi/./Waseda Univ.), Masaki Ito, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Masafumi Onouchi, Kunio Uchiyama (Hitachi), Toshihiko Odaka (Hitachi/./Waseda Univ.), Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta (Renesas Technology), Yasutaka Wada, Keiji Kimura, Hironori Kasahara (Waseda Univ.) SDM2007-143 ICD2007-71
This paper describes a heterogeneous multi-core processor (HMCP) architecture which integrates general purpose processor... [more] SDM2007-143 ICD2007-71
pp.11-16
 Results 1 - 8 of 8  /   
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