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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 7 of 7  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] 2015-03-07
14:15
Kagoshima   Speed Up co-Simulation for Verification of Embedded Systems
Hiroaki Nakata, Kenta Morishima, Yasuo Sugure (Hitachi) CPSY2014-183 DC2014-109
In order to apply co-simulation method to verification of many embedded systems, we speeded up co-simulation between a m... [more] CPSY2014-183 DC2014-109
pp.137-142
CPSY 2011-10-21
09:30
Hyogo   Dependability evaluation of processor using the dependable SRAM by system-level fault injection
Yusuke Takeuchi, Yohei Nakata (Kobe Univ.), Yasuhiro Ito, Yasuo Sugure, Shigeru Oho (Hitachi), Shunsuke Okumura, Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST) CPSY2011-25
We propose a fault-injection system (FIS) that can inject faults such as read/write margin failures and soft errors into... [more] CPSY2011-25
pp.1-6
CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] 2011-03-19
11:45
Okinawa   Virtual HILS -- Efficient software validation by entire system virtualization --
Yasuhiro Ito, Yasuo Sugure, Shigeru Oho (HItachi) CPSY2010-76 DC2010-75
 [more] CPSY2010-76 DC2010-75
pp.243-247
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2010-12-01
09:50
Fukuoka Kyushu University Fault-Injection using Virtualized Environment for Validating Automotive Systems
Yasuhiro Ito (Hitachi.), Yohei Nakata, Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST), Yasuo Sugure, Shigeru Oho (Hitachi.) VLD2010-73 DC2010-40
Fault Injection System: a system level co-simulation environment with fault-injection in memory access was developed. It... [more] VLD2010-73 DC2010-40
pp.119-123
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2010-12-01
10:10
Fukuoka Kyushu University Evaluation and Verification of Dependable Processor Architecture Using System-Level Fault-Injection Scheme
Yohei Nakata (Kobe Univ.), Yasuhiro Ito, Yasuo Sugure, Shigeru Oho (Hitachi Ltd.), Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST) VLD2010-74 DC2010-41
We develop a fault case generator that can generate memory failures in aprocessor-in-the-loop simulation. The fault inje... [more] VLD2010-74 DC2010-41
pp.125-130
VLD 2009-03-11
13:00
Okinawa   [Invited Talk] Model-Based Development for automotive control systems -- Modeling Technique of microcontroller --
Yasuo Sugure, Shigeru Oho (Hitachi Ltd.) VLD2008-129
 [more] VLD2008-129
pp.17-22
IE, SIP, ICD, IPSJ-SLDM 2004-10-22
11:15
Yamagata   Low-Latency and Small-Code-Size Microcontroller Core for Automotive, Industrial, and PC-Peripheral Applications
Yasuo Sugure (Hitachi), Seiji Takeuchi (Renesas), Yuichi Abe, Hiromichi Yamada (Hitachi), Kazuya Hirayanagi, Akihiko Tomita, Kesami Hagiwara, Takeshi Kataoka (Renesas), Takanori Shimura (Hitachi)
A 32-bit embedded RISC microcontroller core targeted for automotive, industrial, and PC-peripheral applications has been... [more] SIP2004-93 ICD2004-125 IE2004-69
pp.25-30
 Results 1 - 7 of 7  /   
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