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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 35件中 1~20件目  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2018-12-14
13:00
Okinawa Miyako Seisyonen-No-Ie On-Chip Delay Measurement for In-field Periodic Test of FPGAs
Yousuke Miyake, Yasuo Sato, Seiji Kajihara (KIT) DC2018-58
Delay-related failures due to aging phenomena are a critical issue of state-of-the-art VLSI systems. In order to detect ... [more] DC2018-58
pp.1-6
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2018-12-06
13:25
Hiroshima Satellite Campus Hiroshima Evaluation of Flexible Test Power Control for Logic BIST in TEG Chips
Takaaki Kato (KIT), Senling Wang (Ehime Univ.), Yasuo Sato, Seiji Kajihara (KIT) VLD2018-57 DC2018-43
Scan-based logic BIST has a crucial problem of high test power dissipation. Its solution requires a flexible test power ... [more] VLD2018-57 DC2018-43
pp.125-130
MW
(2nd)
2018-06-27
- 2018-06-29
Overseas KMITL, Bangkok, Thailand Cross-couple DTMOS Rectifier with Floating sub-circuit using 65nm SOTB CMOS technology for uW RF Energy Harvesting
Shiho Takahashi, Thuy Linh Nguyen, Yasuo Sato, Koichiro Ishibashi (The University of Electro-Communications)
This paper presents a design and evaluations of cross-couple rectifier with floating sub-circuit using DTMOS (Dynamic Th... [more]
DC 2017-12-15
15:30
Akita Akita Study Center, The Open University of Japan A Test Clock Observation Method Using Time-to-Digital Converters for Built-In Self-Test in FPGAs
Yousuke Miyake, Yasuo Sato, Seiji Kajihara (KIT) DC2017-75
A delay measurement method combining a logic BIST with a variable test clock has been proposed to improve field reliabil... [more] DC2017-75
pp.37-42
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-07
09:00
Kumamoto Kumamoto-Kenminkouryukan Parea Flip-Flop Selection for Multi-Cycle Test with Partial Observation in Scan-Based Logic BIST
Shigeyuki Oshima, Takaaki Kato (Kyutech), Senling Wang (Ehime Univ.), Yasuo Sato, Seiji Kajihara (Kyutech) VLD2017-41 DC2017-47
A logic BIST scheme using multi-cycle test with partial observation has been proposed. In the scheme, the selection of f... [more] VLD2017-41 DC2017-47
pp.85-90
CPSY, DC, IPSJ-ARC
(Joint) [detail]
2017-07-26
16:15
Akita Akita Atorion-Building (Akita) A Two-Temperature-Point Calibration Method for A Digital Temperature And Voltage Sensor
Yousuke Miyake, Yasuo Sato, Seiji kajihara (KIT) DC2017-19
A measurement method of a digital sensor using ring oscillators to measure a temperature and a voltage of a VLSI was pro... [more] DC2017-19
pp.19-24
DC 2016-12-16
13:00
Yamagata Sakata Sogo-Bunka Center(Sakata-City) High Reliable Memory Architecture with Adaptive Combination of Aging-Aware In-Field Self-Repair and ECC
Gian Mayuga, Yuta Yamato (NAIST), Yasuo Sato (KIT), Michiko Inoue (NAIST) DC2016-64
 [more] DC2016-64
pp.1-6
DC 2015-12-18
13:20
Niigata Kurieito Mulakami (Murakami City) On Measurement of On-Chip Temperature And Voltage Variation Using A Digital Monitor
Yousuke Miyake, Takaaki Kato, Takuya Itonaga, Yasuo Sato, Seiji Kajihara (KIT) DC2015-74
A digital monitor for measuring a temperature and a voltage of VLSIs is proposed. The monitor can derive measurement res... [more] DC2015-74
pp.5-10
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-03
10:50
Nagasaki Nagasaki Kinro Fukushi Kaikan On Correction of Temperature Influence to Delay Measurement in FPGAs
Takeru Kina, Yousuke Miyake, Yasuo Sato, Seiji Kajihara (KIT) VLD2015-63 DC2015-59
As a means for delay testing for VLSIs in field, a measurement method of a path delay for a logic circuit using variable... [more] VLD2015-63 DC2015-59
pp.165-170
DC 2014-12-19
13:00
Toyama   Study on reduction and control of NBTI-induced degradation in FPGA-based ring oscillators
Yasuo Sato, Yousuke Miyake, Seiji Kajihara (Kyutech) DC2014-67
Ring oscillators are used for variety of applications to enhance reliability on LSIs or FPGAs; however, the performance ... [more] DC2014-67
pp.1-6
DC 2014-12-19
13:25
Toyama   A Temperature Monitor Using Ring-Oscillators on FPGA
Yousuke Miyake, Yasuo Sato, Seiji Kajihara (kyutech) DC2014-68
On-chip temperature monitors are often used to guarantee the reliability of VLSIs and monitors using ring oscillators ha... [more] DC2014-68
pp.7-12
DC 2014-12-19
14:15
Toyama   Reliability of ECC-based Memory Architectures with Online Self-repair Capabilities
Gian Mayuga, Yuta Yamato, Tomokazu Yoneda (NAIST), Yasuo Sato (Kyutech), Michiko Inoue (NAIST) DC2014-70
 [more] DC2014-70
pp.19-24
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-28
14:45
Oita B-ConPlaza On-chip delay measurement for FPGAs
Kentaro Abe, Yousuke Miyake, Seiji Kajihara, Yasuo Sato (KIT) VLD2014-109 DC2014-63
This paper describes an on-chip delay measurement method that targets a logic circuit on an FPGA. While advances in semi... [more] VLD2014-109 DC2014-63
pp.245-250
DC 2014-06-20
14:30
Tokyo Kikai-Shinko-Kaikan Bldg. Capture Power Evaluation for A Low Power BIST Method Using A TEG Chip
Toshiya Nishida (Kyushu Inst. of Tech.), Senling Wang (Ehime Univ.), Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.) DC2014-13
Voltage drop by a momentary current change during capture cycles in scan-based testing brings an increase in path delay ... [more] DC2014-13
pp.21-26
DC 2013-12-13
13:25
Ishikawa   Variable Test-Timing Generation for Built-In Self-Test on FPGA
Yasuo Sato, Munehiro Matsuura, Hitoshi Arakawa, Yousuke Miyake, Seiji Kajihara (Kyushu Inst. of Tech.) DC2013-69
This paper proposes a variable test-timing generation method that should be used for built-in self-test on FPGA. Applica... [more] DC2013-69
pp.7-12
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2013-11-28
13:45
Kagoshima   A Study on Design Structure of Ring Oscillators with Plural Frequency Characteristics in FPGAs
Yousuke Miyake, Masafumi Monden, Yasuo Sato, Seiji Kajihara (Kyusyu Inst. of Tech.) VLD2013-84 DC2013-50
FPGAs are used in various embedded systems including highly reliable systems, therefore, it is important to ensure its r... [more] VLD2013-84 DC2013-50
pp.165-170
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2013-11-29
08:30
Kagoshima   A Study of Burn-In Test Prediction by Data Mining
Satoshi Nonoyama, Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.), Yoshiyuki Nakamura (Renesas Electronics) VLD2013-91 DC2013-57
 [more] VLD2013-91 DC2013-57
pp.221-226
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2013-11-29
09:20
Kagoshima   Design and evaluation of circuits to control scan-in power in logic BIST
Takaaki Kato, Takeru Kina, Yousuke Miyake, Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.) VLD2013-93 DC2013-59
Power reduction during Logic BIST is a crucial problem; however, power controlling technologies are required as well as ... [more] VLD2013-93 DC2013-59
pp.233-238
DC 2013-06-21
14:45
Tokyo Kikai-Shinko-Kaikan Bldg. A theretical discussion for testabilty of a degraded LSI in field
Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.) DC2013-12
Various electronic systems that consist of variety of LSIs require very high reliability in field. However, physical deg... [more] DC2013-12
pp.13-18
DC 2013-02-13
16:15
Tokyo Kikai-Shinko-Kaikan Bldg. Temperature and voltage estimation considering manufacturing variability for a monitoring circuit
Yousuke Miyake, Wataru Tsumori, Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.), Yukiya Miura (Tokyo Metropolitan Univ.) DC2012-89
Delay increase due to aging phenomena is a critical issue of VLSIs. For detecting such increase in field, a highly accur... [more] DC2012-89
pp.55-60
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