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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 7 of 7  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
CS, CAS 2020-02-27
14:05
Kumamoto   [Invited Lecture] Implementation of a Software-based Time-aware Shaper for TSN
Yasin Oge, Yuta Kobayashi, Takahiro Yamaura, Tomonori Maegawa (Toshiba) CAS2019-106 CS2019-106
In this lecture, we present the design, implementation, and evaluation of a time-aware shaper, which is a traffic shaper... [more] CAS2019-106 CS2019-106
pp.49-54
NS 2019-01-18
14:35
Nagasaki Nagasaki Prefectural Art Museum [Encouragement Talk] Timing-Accuracy Evaluation of a Time-aware Shaper for IEEE 802.1Qbv using Time-based Transmission Scheme
Yasin Oge, Yuta Kobayashi, Takahiro Yamaura, Tomonori Maegawa (Toshiba) NS2018-186
This paper presents an implementation and evaluation of a time-aware shaper, a traffic shaper specifically designed for ... [more] NS2018-186
pp.47-52
NS 2018-05-18
10:20
Kanagawa Yokohama City Education Center Implementation and Evaluation of a Time-aware Shaper for IEEE 802.1Qbv using Time-based Transmission Scheme
Yasin Oge, Yuta Kobayashi, Takahiro Yamaura, Tomonori Maegawa (Toshiba) NS2018-25
This paper presents an implementation and evaluation of a time-aware shaper, a traffic shaper specifically designed for ... [more] NS2018-25
pp.57-62
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2016-03-25
14:30
Nagasaki Fukue Bunka Hall/Rodou Fukushi Center Design Evaluation of Low-Latency Handshake Join on FPGA
Masato Yoshimi, Yasin Oge, Celimuge Wu, Tsutomu Yoshinaga (UEC) CPSY2015-155 DC2015-109
This work revisits the processing of sliding-window joins on FPGAs. In this paper, we propose an FPGA-based implementati... [more] CPSY2015-155 DC2015-109
pp.253-258
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] 2016-01-19
17:45
Kanagawa Hiyoshi Campus, Keio University FPGA-based Parallel Processing of Sliding-Window Aggregate Queries on Data Streams
Yoshimitsu Ogawa, Yasin Oge, Masato Yoshimi, Celimuge Wu, Tsutomu Yoshinaga (UEC) VLD2015-86 CPSY2015-118 RECONF2015-68
In this report, we present an evaluation of Configurable Query Processing Hardware (CQPH) implemented on multiple FPGAs.... [more] VLD2015-86 CPSY2015-118 RECONF2015-68
pp.79-84
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
14:00
Kanagawa Hiyoshi Campus, Keio University Acceleration of Big Data Partitioning with Multiple FPGA boards
Ryu Kudo, Saori Sudo, Yasin Oge (UEC), Yuta Terada (AVAL DATA), Masato Yoshimi, Hidetsugu Irie, Tsutomu Yoshinaga (UEC) VLD2014-143 CPSY2014-152 RECONF2014-76
Data volume and diversity that we treat have been increasing rapidly because of increasing popularity of the internet an... [more] VLD2014-143 CPSY2014-152 RECONF2014-76
pp.193-198
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-17
10:00
Kanagawa   FPGA-based Implementation of Sliding-Window Aggregates over Disordered Data Streams
Yasin Oge, Masato Yoshimi (Univ. of Electro-Comm.), Takefumi Miyoshi (e-trees), Hideyuki Kawashima (Univ. of Tsukuba), Hidetsugu Irie, Tsutomu Yoshinaga (Univ. of Electro-Comm.) VLD2012-125 CPSY2012-74 RECONF2012-79
This paper proposes an order-agnostic implementation of sliding-window aggregate queries on an FPGA. Instead of bufferin... [more] VLD2012-125 CPSY2012-74 RECONF2012-79
pp.105-110
 Results 1 - 7 of 7  /   
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