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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 6 of 6  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM 2019-10-24
Miyagi Niche, Tohoku Univ. [Invited Talk] Random nanostructure formation and electric readout for nano-artifact metrics
Seiya Kasai, Renpeng Lu, Katsumi Shimizu, Xiang Yin (Hokkaido Univ.), Yosuke Ueba, Mikio Ishikawa, Mitsuru Kitamura (DNP), Morihisa Hoga (AIST), Makoto Naruse (Univ. of Tokyo), Tsutomu Matsumoto (YNU) SDM2019-62
We introduce a basic concept of nano-artifact metrics, expected to be a highly secure authentication technique using nan... [more] SDM2019-62
SDM, ED, CPM 2019-05-17
Shizuoka Shizuoka Univ. (Hamamatsu) Experimental Study on Optimization of 2D Random Nanostructure Formation and Electrical Readout for Nano Artifact Metrics
Renpeng Lu, Katsumi Shimizu, Xiang Yin (Hokkaido Univ.), Yosuke Ueba, Mikio Ishikawa, Mitsuru Kitamura (DNP), Seiya Kasai (Hokkaido Univ.) ED2019-24 CPM2019-15 SDM2019-22
For nano-artifact metrics utilizing resist collapse in nanometer-scale electron beam lithography, we investigate lithogr... [more] ED2019-24 CPM2019-15 SDM2019-22
ED, SDM 2016-03-03
Hokkaido Centennial Hall, Hokkaido Univ. Nonlinear voltage transfer characteristics of a graphene three-branch nano-junction device and its control
Xiang Yin (Hokkaido Univ.), Polin Liu, Hirofumi Tanaka (Kyushu Inst. of Tech.), Toshihiko Maemoto (Osaka Inst. of Tech.), Seiya Kasai (Hokkaido Univ.) ED2015-126 SDM2015-133
 [more] ED2015-126 SDM2015-133
CPM, ED, SDM 2014-05-29
Aichi   Characterization and analysis of hysteresis properties in insulated-gate GaAs-based nanowire FETs
Ryota Kuroda, Xiang Yin, Masaki Sato, Seiya Kasai (Hokkaido Univ.) ED2014-36 CPM2014-19 SDM2014-34
We fabricate SiN- and Al2O3-gate GaAs etched nanowire FETs, characterized dynamic hysteresis properties in their transfe... [more] ED2014-36 CPM2014-19 SDM2014-34
SDM, ED 2013-02-27
Hokkaido Hokkaido Univ. Fabrication of Graphene-based Three-branch Nano-junction (TBJ) and Its Application to Logic Circuits
Xiang Yin, Seiya Kasai (Hokkaido Univ.) ED2012-134 SDM2012-163
A graphene-based three-branch nano-junction (TBJ) devices is investigated for its application to Boolean logic gates. Ow... [more] ED2012-134 SDM2012-163
Okinawa Okinawa Seinen-kaikan [Invited Talk] Nonlinear Three Branch Nano-Junction Devices and Their Application to Logic Circuits
Seiya Kasai (Hokkaido Univ.), Shaharin Fadzli Abd Rahman (UTM/Hokkaido Univ.), Masaki Sato, Xiang Yin (Hokkaido Univ.), Toshihiko Maemoto (Osaka Inst. Tech.)
A nanometer-scale semiconductor three-branch junction (TBJ) structure exhibits an unique nonlinear voltage transfer char... [more]
 Results 1 - 6 of 6  /   
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