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 Results 1 - 6 of 6  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
RCS, AN, MoNA, SR
(Joint)		 2009-03-04
13:00		 Kanagawa YRP MIMO-OFDM Maximum Likelihood Detector Employing Spatio-Temporal Filters to Supress Co-Channel Interference
Tsuyoshi Terao, Kazuhiko Fukawa, Satoshi Suyama, Hiroshi Suzuki (Tokyo Inst. of Tech.) RCS2008-220		 This report proposes a reception scheme for a MIMO-OFDM downlink system that performs the maximum likelihood detection u... [more] RCS2008-220
pp.47-52
RCS, AN, MoNA, SR
(Joint)		 2009-03-04
13:20		 Kanagawa YRP Minimum BER-based MIMO-OFDM Precoding Scheme under Co-Channel Interference
Tsuyoshi Terao, Kazuhiko Fukawa, Satoshi Suyama, Hiroshi Suzuki (Tokyo Inst. of Tech.) RCS2008-221		 In a MIMO-OFDM downlink system, a reception scheme that performs the maximum likelihood detection using spatio-temporal ... [more] RCS2008-221
pp.53-58
SR 2008-07-31
16:40		 Tokyo NICT (Koganei,-city Tokyo) [Technology Exhibit] FPGA Implementation of Gaussian Multicarrier Transceiver and Its Evaluation
Tsuyoshi Terao, Tetsuou Ohori, Junichi Onodera, Kenji Goto, Satoshi Suyama, Hiroshi Suzuki (Tokyo Inst. of Tech.) SR2008-29		 This report investigates the feasibility of the implementation of Gaussian multicarrier (GMC) transceiver, which shapes ... [more] SR2008-29
pp.73-78
RCS, AN, MoNA, SR, WBS
(Joint)		 2008-03-06
13:40		 Kanagawa YRP Feasibility Investigation of Gaussian Multicarrier Transmitter via FPGA Implementation
Tetsuou Ohori, Junichi Onodera, Kenji Goto, Tsuyoshi Terao, Satoshi Suyama, Hiroshi Suzuki (Tokyo Inst. of Tech.) RCS2007-220		 This report shows that a real-time Gaussian multicarrier (GMC) transmitter can be implemented on an FPGA board in order ... [more] RCS2007-220
pp.205-210
SR 2007-07-27
16:55		 Kanagawa   Studies on the Phase Noise and Spurious Level Behavior of an All Digital Phase Locked Loop
Michael Zamrowski (Johannes Gutenberg Univ.), Tsuyoshi Terao, Kiyomichi Araki (Tokyo Inst. of Tech.) SR2007-45		 An All Digital Phase Locked Loop (ADPLL) was proposed being suitable for a CMOS processed system on one chip digital RF ... [more] SR2007-45
pp.157-162
MW, SCE 2007-04-27
09:00		 Tokyo Kikai-Shinko-Kaikan Bldg. Phase Noise and Spurious Level Characteristics in All-Digital PLL
Tsuyoshi Terao, Kiyomichi Araki (Tokyo Inst. of Tech.) SCE2007-1 MW2007-1		 All-Digital PLL(ADPLL) has been proposed for local oscillators of digital RF transceivers, which are suitable for CMOS s... [more] SCE2007-1 MW2007-1
pp.1-6
 Results 1 - 6 of 6  /   
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