Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
DC |
2019-02-27 15:10 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
State Encoding with Stochastic Numbers for Transient Fault Tolerant Linear Finite State Machines Yuki Maeda, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ.) DC2018-81 |
Stochastic Computing (SC) has attractive characteristics, compared with deterministic (or general binary) computing, suc... [more] |
DC2018-81 pp.61-66 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 14:15 |
Hiroshima |
Satellite Campus Hiroshima |
Register-Transfer Level Exploration of Segments Utilizable for Scan Path Synthesis Sho Yuasa, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2018-59 DC2018-45 |
[more] |
VLD2018-59 DC2018-45 pp.137-142 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 10:30 |
Kumamoto |
Kumamoto-Kenminkouryukan Parea |
Stochastic Number Generation with Internal Signals of Peripheral Logic Circuits Naoya Kubota, Maki Fujiha, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ.) VLD2017-47 DC2017-53 |
Stochastic computing (SC), which is an approximate computation with probabilities, has attracted at- tention because it ... [more] |
VLD2017-47 DC2017-53 pp.115-120 |
VLD |
2017-03-03 13:00 |
Okinawa |
Okinawa Seinen Kaikan |
An Approach to Logic Optimization Using Permissible Functions for Error-Tolerant Application Shinya Iwasaki, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ.) VLD2016-128 |
Error-tolerant application, such as image processing, machine learning and so on, is application that can tolerate speci... [more] |
VLD2016-128 pp.145-150 |
VLD |
2017-03-03 13:50 |
Okinawa |
Okinawa Seinen Kaikan |
Architecture of Multiply-Accumulate Operation with Stochastic Iteration Tatsuyoshi Sugino, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ.) VLD2016-130 |
Stochastic computing, which is an approximate computation method with probabilities (called stochastic numbers), draws a... [more] |
VLD2016-130 pp.157-162 |
DC |
2017-02-21 14:00 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Impact of Operational Unit Binding on Aging-induced Degradation in High-level Synthesis for Asynchronous Systems Tsuyoshi Iwagaki, Kohta Itani, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2016-78 |
This paper discusses delay-robustness of a four-phase dual-rail asynchronous system at register transfer level (RTL). A ... [more] |
DC2016-78 pp.23-28 |
DC |
2016-06-20 13:50 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
On State Assignment of Finite State Machines for Soft Error Resilient Stochastic Computing Motoi Fukuda, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ.) DC2016-11 |
Stochastic computing (SC), which is an approximate computation with probabilities, has attracted at- tention owing to it... [more] |
DC2016-11 pp.7-12 |
DC |
2016-02-17 11:30 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Acceleration of Stochastic Computing by Dynamically Sharing Consecutive Bit Sequences Kensuke Takamori, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ.) DC2015-89 |
Stochastic computing, which is a computational scheme with probabilities, is notable for its applicability to error tole... [more] |
DC2015-89 pp.19-24 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 09:20 |
Nagasaki |
Nagasaki Kinro Fukushi Kaikan |
A Handshake-delay-aware Scheduling Algorithm in High-level Synthesis for Four-phase Dual-rail Asynchronous Systems Kohta Itani, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2015-60 DC2015-56 |
This report is intended to discuss the scheduling problem in high-level synthesis~(HLS) for four-phase dual-rail asynchr... [more] |
VLD2015-60 DC2015-56 pp.147-152 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 16:40 |
Oita |
B-ConPlaza |
Don't-Care Extension in Logic Synthesis for Error Tolerant Application Tomoya Inaoka, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ.) VLD2014-89 DC2014-43 |
In logic synthesis for error tolerant applications, external observability don’t-cares can be freely enhanced within a g... [more] |
VLD2014-89 DC2014-43 pp.123-128 |
VLD |
2014-03-04 11:35 |
Okinawa |
Okinawa Seinen Kaikan |
Effect of Correlated Stochastic Numbers on Calculation Accuracy Shota Ishii, Daiki Sunamori, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ.) VLD2013-147 |
Stochastic computing, which is a computing method with probabilities(called stochastic numbers), draws attention as an a... [more] |
VLD2013-147 pp.79-84 |
DC |
2014-02-10 16:40 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
An Implementation of Fault Tolerant Systems with Mutual Reconfiguration Based on Dual-FPGA Architecture Takuma Mori, Shoichi Ohmoto, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2013-90 |
This work presents a design of fault tolerant systems with mutual reconfiguration based on Dual-FPGA architecture.
The ... [more] |
DC2013-90 pp.67-72 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 15:20 |
Kagoshima |
|
A controller design in high-level synthesis for multi-cycle transient fault tolerance Yutaro Ishimori, Tatsuya Nakaso, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2013-68 DC2013-34 |
This work discusses a design of the controller in a multi-cycle transient
fault tolerant system. It focuses especially ... [more] |
VLD2013-68 DC2013-34 pp.45-50 |
VLD |
2013-03-04 13:50 |
Okinawa |
Okinawa Seinen Kaikan |
A Logic Simplification Algorithm with Multiple Stuck-at Faults for Error Tolerant Application Junpei Kamei, Shingo Matsuki, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2012-136 |
In error tolerant applications, some specific errors, which are of certain types or have severities within certain limit... [more] |
VLD2012-136 pp.1-6 |
DC |
2013-02-13 10:00 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
A Hardware Implementation of a SAT Solver for Test Generation with Solution Reuse Toshiya Mukai, Kenji Ueda, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2012-80 |
[more] |
DC2012-80 pp.1-6 |
DC |
2013-02-13 15:50 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
A Method of Acceptable Fault Identification with Necessary Assignment in Logic Simplification for Error Tolerant Application Shingo Matsuki, Junpei Kamei, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2012-88 |
In error tolerant applications, some specific errors, which are of certain types or have severities within certain limit... [more] |
DC2012-88 pp.49-54 |
DC |
2012-12-14 16:00 |
Fukui |
Aossa (Fukui) |
A Test Generation Model for Over-testing Alleviation and Its Application to Testing Based on Fault Acceptability Masaaki Sakurada, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (HCU) DC2012-77 |
Over-testing, which is to judge fault-free chips as faulty ones, is a cause of the decrease in the effective yield of ch... [more] |
DC2012-77 pp.21-26 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 13:00 |
Fukuoka |
Centennial Hall Kyushu University School of Medicine |
Effective Orderings of Instances and Variable Assignments in SAT-based ATPG with Solution Reuse Kenji Ueda, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2012-83 DC2012-49 |
This report discusses the efficiency of iteratively solving various instances with
solution reuse in test generation ba... [more] |
VLD2012-83 DC2012-49 pp.141-146 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 13:25 |
Fukuoka |
Centennial Hall Kyushu University School of Medicine |
A Heuristic Algorithm for Operational Unit Binding in Transient Fault Tolerant Datapath Synthesis Tatsuya Nakaso, Ryoko Ohkubo, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2012-84 DC2012-50 |
Due to the increase in the integration, operational speed and application complexity,
the tolerance for transient faul... [more] |
VLD2012-84 DC2012-50 pp.147-152 |
DC |
2012-06-22 13:50 |
Tokyo |
Room B3-1 Kikai-Shinko-Kaikan Bldg |
A Study on Fault Tolerant Test Pattern Generators for Reliable Built-in Self Test Yuki Fukazawa, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2012-11 |
In the BIST (built-in self-test) scheme, the occurrence of faults in BIST circuits, such as TPGs (test pattern generator... [more] |
DC2012-11 pp.15-20 |