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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 83  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2022-03-10
10:30
Online Online A Don't Care Filling Method of Control Signals for Concurrent Logical Fault Testing
Haofeng Xu, Toshinori Hosokawa, Hiroshi Yamazaki, Masayuki Arai (Nihon Univ), Masayoshi Yoshimura (KSU) CPSY2021-56 DC2021-90
In recent years, with the increase in test cost for VLSIs, it has been important to reduce the number of test patterns. ... [more] CPSY2021-56 DC2021-90
pp.67-72
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2022-03-10
10:50
Online Online A Test Generatoin Method to Improve Diagonostic Resolution Based on Fault Sensitization Coverage
Yuya Chida, Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meiji Univ.) CPSY2021-57 DC2021-91
As one of test generation methods to achieve high defect coverage, n-detection test generation methods have been propose... [more] CPSY2021-57 DC2021-91
pp.73-78
DC 2022-03-01
13:45
Tokyo Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online)
A Logic Locking Method based on SFLL-hd at Register Transfer Level
Yohei Noguchi, Masayoshi Yoshimura (Kyoto Sangyo Univ.), Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.) DC2021-72
In recent years, with the increase of VLSI integration, LSI design companies utilize circuit design information, called ... [more] DC2021-72
pp.45-50
DC 2022-03-01
15:10
Tokyo Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online)
State assignment method to improve transition fault coverage for controllers including invalid states
Kyohei Iizuka, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ) DC2021-75
 [more] DC2021-75
pp.63-68
DC 2022-03-01
15:45
Tokyo Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online)
Evaluation of Don't Care Filling Method of Control Signals to Enhance Fault Diagnosability for Logic and Timing Fault
Kohei Tsuchibuchi, Xu Haofeng, Yuya Chida, Toshinori Hosokawa (Nihon Univ), Koji Yamazaki (Meiji Univ) DC2021-76
 [more] DC2021-76
pp.69-74
DC 2022-03-01
16:10
Tokyo Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online)
An Estimation Method of Defect Types for Multi-cycle Capture Testing Using Artificial Neural Networks and Fault Detection Information
Natsuki Ota, Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meiji Univ.), Masayuki Arai, Yukari Yamauchi (Nihon Univ.) DC2021-77
 [more] DC2021-77
pp.75-80
DC 2021-12-10
13:00
Kagawa
(Primary: On-site, Secondary: Online)
A Low Power Oriented Multiple Target Test Generation Method
Rei Miura, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.), Masayuki Arai (Nihon Univ.) DC2021-55
In recent years, since capture power consumption for VLSIs significantly increases in at-speed scan testing, low capture... [more] DC2021-55
pp.1-6
DC 2021-12-10
14:00
Kagawa
(Primary: On-site, Secondary: Online)
A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level
Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2021-57
In recent years, to meet strict time-to-market constraints, it has become difficult for only one semiconductor design co... [more] DC2021-57
pp.13-18
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2021-03-26
11:00
Online Online An Estimation Method of a Defect Types for Suspected Fault Lines in Logical Faulty VLSI Using Neural Networks
Natsuki Ota, Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meiji Univ.), Yukari Yamauchi, Masayuki Arai (Nihon Univ.) CPSY2020-61 DC2020-91
Since fault diagnosis methods for specified fault models might cause misprediction and non-prediction, a fault diagnosis... [more] CPSY2020-61 DC2020-91
pp.67-72
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2021-03-26
11:20
Online Online A Don't Care Filling Method of Control Signals for Controllers to Enhance Fault Diagnosability at Register Transfer Level
Kohei Tsuchibuchi, Toshinori Hosokawa (Nihon Univ), Koji Yamazaki (Meiji Univ.) CPSY2020-62 DC2020-92
With the progress of semiconductor technology in recent years, fault analysis is important to improve the yield of VLSIs... [more] CPSY2020-62 DC2020-92
pp.73-78
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2021-03-26
11:40
Online Online A Controller Augmentation method to Improving Transition Fault Coverage
Kyohei Iizuka, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ) CPSY2020-63 DC2020-93
With shrinking feature sizes, growing clock frequencies, and decreasing power supply voltage, modern VLSIs are increasin... [more] CPSY2020-63 DC2020-93
pp.79-84
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2021-03-26
12:00
Online Online A Logic Locking Method Based on Anti-SAT at Register Transfer Level
Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) CPSY2020-64 DC2020-94
In recent years, increasing circuit density, it has become difficult for only one semiconductor design company to design... [more] CPSY2020-64 DC2020-94
pp.85-90
DC 2021-02-05
14:00
Online Online Multiple Target Test Generation Method using Test Scheduling Information of RTL Hardware Elements
Ryuki Asami, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ), Masayuki Arai (Nihon Univ) DC2020-74
In recent years, since the test cost for large-scale integrated circuits has increased, design-for-testability methods f... [more] DC2020-74
pp.30-35
DC 2021-02-05
14:50
Online Online A Test Generation Method Using Information of Easily Testable Functional Time Expansion Model
Kenta Nakamura, Yuta Ishiyama, Toshinori Hosokawa (Nihon Univ.) DC2020-76
 [more] DC2020-76
pp.42-47
DC 2021-02-05
15:30
Online Online A Don't Care Filling Method of Control Signals Based on Non-scan Field Testability at Register Transfer Level
Yuki Ikegaya, Yuta Ishiyama, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2020-77
A field testing that monitors the values of circuit outputs and internal signal lines during function mode is used as on... [more] DC2020-77
pp.48-53
CPSY, DC, IPSJ-ARC [detail] 2020-07-31
15:45
Online Online A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the number of Test Patterns
Ryuki Asami, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.) CPSY2020-12 DC2020-12
In recent years, as the high density and complexity of integrated circuits have increased, defects in cells have increas... [more] CPSY2020-12 DC2020-12
pp.75-80
CPSY, DC, IPSJ-ARC [detail] 2020-07-31
16:15
Online Online A Generation Method of Easily Testable Functional Time Expansion Models Using Testability Measure Based on Data Amount
Kenta Nakamura, Toshinori Hosokawa, Yuta Ishiyama (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) CPSY2020-13 DC2020-13
 [more] CPSY2020-13 DC2020-13
pp.81-86
CPSY, DC, IPSJ-ARC [detail] 2020-07-31
17:30
Online Online An Area Reduction Oriented Controller Augmentation Method Based on Functionally Equivalent Finite State Machine Generation
Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) CPSY2020-15 DC2020-15
In recent year, controller augmentation has been used for design-for-testability and design-for-security at register tra... [more] CPSY2020-15 DC2020-15
pp.93-98
HWS, VLD [detail] 2020-03-06
14:30
Okinawa Okinawa Ken Seinen Kaikan
(Cancelled but technical report was issued)
A Test Generation Method for Resistive Open Faults Using Partial MAX-SAT solver
Hiroshi Yamazaki, Yuta Ishiyama, Tatsuma Matsuta, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2019-131 HWS2019-104
In VLSI testing, stuck-at fault model and transition fault model have been widely used. However, with advance of semicon... [more] VLD2019-131 HWS2019-104
pp.215-220
DC 2020-02-26
12:00
Tokyo   A controller augmentation method to reduce the number of untestable faults for multiplexers with n-inputs
Yuki Takeuchi, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2019-90
With the complexity for VLSIs, transition fault testing is required. However, VLSIs generally have more untestable trans... [more] DC2019-90
pp.25-30
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