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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 18 of 18  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
HWS 2019-04-12
15:05
Miyagi Tohoku University Implementation and Experimental Evaluation of Physically Unclonable Functions in 180nm CMOS Process
Mitsuru Shiozaki, Takaya Kubota, Masayoshi Shirahata (Ritsumeikan Univ.), Yohei Hori, Toshihiro Katashita (AIST), Takeshi Fujino (Ritsumeikan Univ.) HWS2019-4
Evaluation items and evaluation schemes of Physically Unclonable Function (PUF) are discussed in international standardi... [more] HWS2019-4
pp.19-24
HWS, VLD 2019-03-01
15:45
Okinawa Okinawa Ken Seinen Kaikan On Machine Learning Attack Tolerance for PUF-based Device Authentication System
Tomoki Iizuka (UTokyo), Yasuhiro Ogasahara, Toshihiro Katashita, Yohei Hori (AIST), Hiromitsu Awano (Osaka Univ.), Makoto Ikeda (UTokyo) VLD2018-133 HWS2018-96
Double-Arbiter PUF (DAPUF) and PL-PUF are known to be highly resistant to machine learning attacks.
In this paper, we p... [more]
VLD2018-133 HWS2018-96
pp.237-242
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]
2016-11-29
11:20
Osaka Ritsumeikan University, Osaka Ibaraki Campus Preliminary experimental platform for FlexPower FPGA evaluation
Toshihiro Katashita, Masakazu Hioki, Yohei Hori, Hanpei Koike (AIST) RECONF2016-47
 [more] RECONF2016-47
pp.41-46
OME 2016-10-28
17:00
Tokyo Kikai-Shinko-Kaikan Bldg. Stability of organic physically unclonable function for voltage fractuation.
Kazunori Kuribara, Yohei Hori, Toshihiro Katashita (AIST), Kazuaki Kakita, Yasuhiro Tanaka (Ube Inds.), Manabu Yoshida (AIST) OME2016-47
We have investigated stability of novel security system. We fabricate organic ring oscillators (ROs) and consider them a... [more] OME2016-47
pp.39-42
RECONF 2015-06-20
11:10
Kyoto Kyoto University A Rapid Verification Environment for Statistical Evaluation of PUF Circuits
Toshihiro Katashita, Yasunori Onda, Yohei Hori (AIST) RECONF2015-18
In this study, we constructed a rapid experimentation environment for Physically Unclonable Function (PUF) circuit verif... [more] RECONF2015-18
pp.97-102
RECONF 2015-06-20
11:35
Kyoto Kyoto University FPGA Implementation of a key generation circuit using PUF and Fuzzy Extractor on SASEBO-G3
Yohei Hori, Toshihiro Katashita (AIST) RECONF2015-19
We implemented a key generation circuit using a Physically Unclonable Function (PUF) and Fuzzy Extractor (FE) to a Kinte... [more] RECONF2015-19
pp.103-108
ISEC 2013-12-11
15:20
Tokyo Kikai-Shinko-Kaikan Bldg. Education for Practical Hardware Security Based on Information Security Education Program
Yu-ichi Hayashi, Naofumi Homma (Tohoku Univ.), Toshihiro Katashita (AIST), Hideaki Sone (Tohoku Univ.) ISEC2013-78
This paper reports an education course for the development of human resources in hardware security in a practical educat... [more] ISEC2013-78
pp.33-37
RECONF 2013-05-21
14:45
Kochi Kochi Prefectural Culture Hall Performance Evaluation of Physical Unclonable FUnctions on Kintex-7 FPGA
Yohei Hori, Toshihiro Katashita, Kazukuni Kobara (AIST) RECONF2013-17
The challenge-response properties of Physical Unclonable Functions (PUFs) on 28-nm process FPGA on the ten
SASEBO-GIII ... [more]
RECONF2013-17
pp.91-96
RECONF 2011-05-13
11:35
Hokkaido Hokkaido Univ. (Faculty of Eng., B3 Bldg.) Power Consumption Evaluation of a Dynamically Reconfigurable Multi-cryptoprocessor on Virtex-5 FPGA
Yohei Hori, Toshihiro Katashita, Akashi Satoh (AIST) RECONF2011-17
 [more] RECONF2011-17
pp.97-102
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2010-12-01
10:10
Fukuoka Kyushu University Magnetic Field Measurement for Side-channel Analysis Environment
Toshihiro Katashita, Yohei Hori, Akashi Satoh (AIST) RECONF2010-46
Cryptography used widely in electronic products is evaluated in terms of computationally-secure, however there is vulner... [more] RECONF2010-46
pp.43-48
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2010-12-01
11:05
Fukuoka Kyushu University A study of the success rate of MIA under various probability density function estimations
Yohei Hori (AIST), Takahiro Yoshida (Aoyama Univ.), Toshihiro Katashita, Akashi Satoh (AIST) RECONF2010-48
The pfrobability density function (PDF) of voltage of AES hardware
module is estimated in various ways and applied to ... [more]
RECONF2010-48
pp.55-60
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2010-12-01
11:25
Fukuoka Kyushu University Performance Evaluation for PUF-based Authentication Systems with Shift Post-processing
Hyunho Kang, Yohei Hori, Toshihiro Katashita, Akashi Satoh (AIST) RECONF2010-49
A physical unclonable function (PUF) is a physical system with a device manufacturing variations and could be useful for... [more] RECONF2010-49
pp.61-64
RECONF 2010-09-17
13:15
Shizuoka Shizuoka University (Faculty of Eng., Hall 2) Quantitative Performance Evaluation of Arbiter PUFs on FPGAs
Yohei Hori (AIST), Takahiro Yoshida (Chuo Univ.), Toshihiro Katashita, Akashi Satoh (AIST) RECONF2010-37
The quantitative performance indicators of Physical Unclonable
Functions (PUFs)---Randomness, Steadiness, Correctness,... [more]
RECONF2010-37
pp.115-120
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2009-12-03
15:40
Kochi Kochi City Culture-Plaza Development of Standard Evaluation Environment for Side-channel Attacks and Countermeasures
Toshihiro Katashita (AIST), Yohei Hori (Chuo Univ.), Akashi Satoh (AIST) RECONF2009-46
Cryptography used widely in electronic products is evaluated in terms of computationally-secure, however there is vulner... [more] RECONF2009-46
pp.31-36
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2008-11-18
15:20
Fukuoka Kitakyushu Science and Research Park Development of Side-channel Attack Standard Evaluation BOard and Tool
Yohei Hori, Toshihiro Katashita, Hirofumi Sakane, Kenji Toda, Akashi Satoh (National Institute of Advanced Industrial Science and Technology), Hideki Imai (Chuo Univ.) RECONF2008-54
Side-channel Attack Standard Evaluation BOards (SASEBO) and their
analysis tools are developed to provide uniform exp... [more]
RECONF2008-54
pp.87-92
ICD, ITE-CE 2007-12-14
14:15
Kochi   Versatile Media Processor for Super High Definition (VMP/SHD) -- The scalable architecture of parallel overlay frame engine --
Kenji Toda, Toshihiro Katashita, Yohei Hori, Osamu Morikawa (AIST) ICD2007-137
 [more] ICD2007-137
pp.101-106
DE, DC 2006-10-17
13:30
Tokyo   Architecture of Hi-speed Network Filtering System
Kenji Toda, Toshihiro Katashita (AIST), Kazumi Sakamaki (Tokyo Metropolitan Industrial Technology Research Institute), Mitsugu Nagoya (DUAXES), Yasunori Terashima (BITS)
 [more] DE2006-122 DC2006-29
pp.19-23
CPSY, DC 2006-04-14
16:10
Tokyo Takeda Hall Versatile media processor utilizing multiple overlay frames -- capable of multi-display and contents-security --
Kenji Toda, Toshihiro Katashita, Yohei Hori, Osamu Morikawa (AIST)
 [more] CPSY2006-11 DC2006-11
pp.61-66
 Results 1 - 18 of 18  /   
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