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Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD, SDM 2008-07-18
Tokyo Kikai-Shinko-Kaikan Bldg. A Sub-μs Wake-up Time Power Gating Technique with Bypass Power Line for Rush Current Support
Koichi Nakayama, Ken-ichi Kawasaki, Tetsuyoshi Shiota, Atsuki Inoue (Fujitsu Lab.) SDM2008-141 ICD2008-51
A sub-$\micro$s wake-up power gating technique was developed for low power SOCs. It uses two types of power switches and... [more] SDM2008-141 ICD2008-51
ICD, ITE-IST 2007-07-26
Hyogo   On-Die Supply-Voltage Noise Sensor with Real-Time Sampling Mode for Low-Power Processor Applications
Tomio Sato, Atsuki Inoue, Tetsuyoshi Shiota, Tomoko Inoue, Yukihito Kawabe, Tetsutaro Hashimoto (Fujitsu Lab.), Toshifumi Imamura, Yoshitaka Murasaka, Makoto Nagata, Atsushi Iwata (A-R-Tec) ICD2007-40
The real time on-die noise sensor reported here can continuously detect up to 100 noise events per a second without dist... [more] ICD2007-40
ICD, SDM 2006-08-17
Hokkaido Hokkaido University A supply voltage adjustment technique for low power consumption and its application to SOCs with multiple threshold voltage CMOS
Hiroshi Okano, Tetsuyoshi Shiota, Yukihito Kawabe (Fujitsu lab.), Wataru Shibamoto (Fujitsu), Tetsutaro Hashimoto, Atsuki Inoue (Fujitsu lab.)
An energy-saving technique for SOCs using multiple threshold voltage CMOS was developed. It uses process sensors and pro... [more] SDM2006-127 ICD2006-81
ICD 2005-05-26
Hyogo Kobe Univ. A Single-Chip Multi-Processor integrating Quadruple Processors on 90nm CMOS Process
Ken-ichi Kawasaki, Tetsuyoshi Shiota, Yukihito Kawabe, Wataru Shibamoto, Atsushi Sato, Tetsutaro Hashimoto, Motoaki Matsumura, Hiroshi Okano, Fumihiko Hayakawa, Shinichiro Tago, Yasuki Nakamura (Fujitsu Labs.), Hideo Miyake (FLT), Atsuhiro Suga, Hiromasa Takahashi, Atsuki Inoue (Fujitsu Labs.)
We have developed a 51.2-GOPS single-chip multi-processor integrating quadruple processors with 1.0-GB/s system-bus dire... [more] ICD2005-21
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