ken-system: - All Technical Committee Conferences

IEICE Technical Committee Submission System
Conference Schedule

Online Proceedings
[Sign in]
Tech. Rep. Archives

[Japanese] / [English]

(

Committee/Place/Topics

) --Press->

(

Paper Keywords: / Column:Title Auth. Affi. Abst. Keyword

) --Press->

All Technical Committee Conferences (Searched in: All Years)

Search Results: Conference Papers

Conference Papers (Available on Advance Programs) (Sort by: Date Descending)

Committee	Date Time	Place		Paper Title / Authors	Abstract	Paper #
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail]	2008-11-18 10:55	Fukuoka	Kitakyushu Science and Research Park	Evaluation of Hardware Algorithms on a Circuit Model Considering Wire Delay Tetsuya Nagase, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ.) VLD2008-77 DC2008-45	In the design of integrated circuits, it is important to design or choose algorithms according to the requirements such ... [more]	VLD2008-77 DC2008-45 pp.103-108
COMP	2007-12-14 14:50	Hiroshima	Hiroshima University	Evaluation of Hardware Algorithm Considering Wire Delay Tetsuya Nagase, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ.) COMP2007-51	Computation time of hardware algorithms has been evaluated with the number of levels of the combinational circuit model.... [more]	COMP2007-51 pp.23-28

Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

[Return to Top Page]

[Return to IEICE Web Page]

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan